mirror of https://github.com/raphnet/4nes4snes
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Raphaël Assénat
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AVR-USB Driver Software License Agreement
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Version 2006-07-24
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||||
THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN
|
||||
ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING
|
||||
THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT.
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||||
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||||
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||||
1 DEFINITIONS
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1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH,
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Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA.
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||||
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||||
1.2 "You" shall mean the Licensee.
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||||
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||||
1.3 "AVR-USB" shall mean the firmware-only USB device implementation for
|
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Atmel AVR microcontrollers distributed by OBJECTIVE DEVELOPMENT and
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||||
consisting of the files usbdrv.c, usbdrv.h, usbdrvasm.S, oddebug.c,
|
||||
oddebug.h, usbdrvasm.asm, iarcompat.h and usbconfig-prototype.h.
|
||||
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||||
|
||||
2 LICENSE GRANTS
|
||||
|
||||
2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source
|
||||
code of AVR-USB.
|
||||
|
||||
2.2 Distribution and Use. OBJECTIVE DEVELOPMENT grants you the
|
||||
non-exclusive right to use and distribute AVR-USB with your hardware
|
||||
product(s), restricted by the limitations in section 3 below.
|
||||
|
||||
2.3 Modifications. OBJECTIVE DEVELOPMENT grants you the right to modify
|
||||
your copy of AVR-USB according to your needs.
|
||||
|
||||
2.4 USB IDs. OBJECTIVE DEVELOPMENT grants you the exclusive rights to use
|
||||
USB Product ID(s) sent to you in e-mail after receiving your payment in
|
||||
conjunction with USB Vendor ID 5824. OBJECTIVE DEVELOPMENT has acquired an
|
||||
exclusive license for this pair of USB identifiers from Wouter van Ooijen
|
||||
(www.voti.nl), who has licensed the VID from the USB Implementers Forum,
|
||||
Inc. (www.usb.org).
|
||||
|
||||
|
||||
3 LICENSE RESTRICTIONS
|
||||
|
||||
3.1 Number of Units. Only one of the following three definitions is
|
||||
applicable. Which one is determined by the amount you pay to OBJECTIVE
|
||||
DEVELOPMENT, see section 4 ("Payment") below.
|
||||
|
||||
Hobby License: You may use AVR-USB according to section 2 above in no more
|
||||
than 5 hardware units. These units must not be sold for profit.
|
||||
|
||||
Entry Level License: You may use AVR-USB according to section 2 above in no
|
||||
more than 150 hardware units.
|
||||
|
||||
Professional License: You may use AVR-USB according to section 2 above in
|
||||
any number of hardware units, except for large scale production ("unlimited
|
||||
fair use"). Quantities below 10,000 units are not considered large scale
|
||||
production. If your reach quantities which are obviously large scale
|
||||
production, you must pay a license fee of 0.10 EUR per unit for all units
|
||||
above 10,000.
|
||||
|
||||
3.2 Rental. You may not rent, lease, or lend AVR-USB or otherwise encumber
|
||||
any copy of AVR-USB, or any of the rights granted herein.
|
||||
|
||||
3.3 Transfer. You may not transfer your rights under this Agreement to
|
||||
another party without OBJECTIVE DEVELOPMENT's prior written consent. If
|
||||
such consent is obtained, you may permanently transfer this License to
|
||||
another party. The recipient of such transfer must agree to all terms and
|
||||
conditions of this Agreement.
|
||||
|
||||
3.4 Reservation of Rights. OBJECTIVE DEVELOPMENT retains all rights not
|
||||
expressly granted.
|
||||
|
||||
3.5 Non-Exclusive Rights. Your license rights under this Agreement are
|
||||
non-exclusive.
|
||||
|
||||
3.6 Third Party Rights. This Agreement cannot grant you rights controlled
|
||||
by third parties. In particular, you are not allowed to use the USB logo or
|
||||
other trademarks owned by the USB Implementers Forum, Inc. without their
|
||||
consent. Since such consent depends on USB certification, it should be
|
||||
noted that AVR-USB will not pass certification because it does not
|
||||
implement checksum verification and the microcontroller ports do not meet
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||||
the electrical specifications.
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||||
|
||||
|
||||
4 PAYMENT
|
||||
|
||||
The payment amount depends on the variation of this agreement (according to
|
||||
section 3.1) into which you want to enter. Concrete prices are listed on
|
||||
OBJECTIVE DEVELOPMENT's web site, usually at
|
||||
http://www.obdev.at/avrusb/license.html. You agree to pay the amount listed
|
||||
there to OBJECTIVE DEVELOPMENT or OBJECTIVE DEVELOPMENT's payment processor
|
||||
or reseller.
|
||||
|
||||
|
||||
5 COPYRIGHT AND OWNERSHIP
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||||
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||||
AVR-USB is protected by copyright laws and international copyright
|
||||
treaties, as well as other intellectual property laws and treaties. AVR-USB
|
||||
is licensed, not sold.
|
||||
|
||||
|
||||
6 TERM AND TERMINATION
|
||||
|
||||
6.1 Term. This Agreement shall continue indefinitely. However, OBJECTIVE
|
||||
DEVELOPMENT may terminate this Agreement and revoke the granted license and
|
||||
USB-IDs if you fail to comply with any of its terms and conditions.
|
||||
|
||||
6.2 Survival of Terms. All provisions regarding secrecy, confidentiality
|
||||
and limitation of liability shall survive termination of this agreement.
|
||||
|
||||
|
||||
7 DISCLAIMER OF WARRANTY AND LIABILITY
|
||||
|
||||
LIMITED WARRANTY. AVR-USB IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
|
||||
KIND. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, OBJECTIVE
|
||||
DEVELOPMENT AND ITS SUPPLIERS HEREBY DISCLAIM ALL WARRANTIES, EITHER
|
||||
EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND
|
||||
NON-INFRINGEMENT, WITH REGARD TO AVR-USB, AND THE PROVISION OF OR FAILURE
|
||||
TO PROVIDE SUPPORT SERVICES. THIS LIMITED WARRANTY GIVES YOU SPECIFIC LEGAL
|
||||
RIGHTS. YOU MAY HAVE OTHERS, WHICH VARY FROM STATE/JURISDICTION TO
|
||||
STATE/JURISDICTION.
|
||||
|
||||
LIMITATION OF LIABILITY. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW,
|
||||
IN NO EVENT SHALL OBJECTIVE DEVELOPMENT OR ITS SUPPLIERS BE LIABLE FOR ANY
|
||||
SPECIAL, INCIDENTAL, INDIRECT, OR CONSEQUENTIAL DAMAGES WHATSOEVER
|
||||
(INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
|
||||
BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR ANY OTHER PECUNIARY
|
||||
LOSS) ARISING OUT OF THE USE OF OR INABILITY TO USE AVR-USB OR THE
|
||||
PROVISION OF OR FAILURE TO PROVIDE SUPPORT SERVICES, EVEN IF OBJECTIVE
|
||||
DEVELOPMENT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN ANY
|
||||
CASE, OBJECTIVE DEVELOPMENT'S ENTIRE LIABILITY UNDER ANY PROVISION OF THIS
|
||||
AGREEMENT SHALL BE LIMITED TO THE AMOUNT ACTUALLY PAID BY YOU FOR AVR-USB.
|
||||
|
||||
|
||||
8 MISCELLANEOUS TERMS
|
||||
|
||||
8.1 Marketing. OBJECTIVE DEVELOPMENT has the right to mention for marketing
|
||||
purposes that you entered into this agreement.
|
||||
|
||||
8.2 Entire Agreement. This document represents the entire agreement between
|
||||
OBJECTIVE DEVELOPMENT and you. It may only be modified in writing signed by
|
||||
an authorized representative of both, OBJECTIVE DEVELOPMENT and you.
|
||||
|
||||
8.3 Severability. In case a provision of these terms and conditions should
|
||||
be or become partly or entirely invalid, ineffective, or not executable,
|
||||
the validity of all other provisions shall not be affected.
|
||||
|
||||
8.4 Applicable Law. This agreement is governed by the laws of the Republic
|
||||
of Austria.
|
||||
|
||||
8.5 Responsible Courts. The responsible courts in Vienna/Austria will have
|
||||
exclusive jurisdiction regarding all disputes in connection with this
|
||||
agreement.
|
||||
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/* Name: usbconfig.h
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* Project: AVR USB driver
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* Author: Christian Starkjohann
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* Creation Date: 2005-04-01
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* Tabsize: 4
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* Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
|
||||
* License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
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||||
* This Revision: $Id: usbconfig-prototype.h,v 1.1 2013-04-25 02:18:15 cvs Exp $
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||||
*/
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#ifndef __usbconfig_h_included__
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#define __usbconfig_h_included__
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/*
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General Description:
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This file is an example configuration (with inline documentation) for the USB
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driver. It configures AVR-USB for an ATMega8 with USB D+ connected to Port D
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bit 2 (which is also hardware interrupt 0) and USB D- to Port D bit 0. You may
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wire the lines to any other port, as long as D+ is also wired to INT0.
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To create your own usbconfig.h file, copy this file to the directory
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containing "usbdrv" (that is your project firmware source directory) and
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rename it to "usbconfig.h". Then edit it accordingly.
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*/
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/* ---------------------------- Hardware Config ---------------------------- */
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#define USB_CFG_IOPORTNAME D
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/* This is the port where the USB bus is connected. When you configure it to
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* "B", the registers PORTB, PINB and DDRB will be used.
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*/
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#define USB_CFG_DMINUS_BIT 0
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/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected.
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* This may be any bit in the port.
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*/
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#define USB_CFG_DPLUS_BIT 2
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/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected.
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* This may be any bit in the port. Please note that D+ must also be connected
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* to interrupt pin INT0!
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*/
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/* #define USB_CFG_CLOCK_KHZ (F_CPU/1000) */
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/* Clock rate of the AVR in MHz. Legal values are 12000, 15000, 16000 or 16500.
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* The 16.5 MHz version of the code requires no crystal, it tolerates +/- 1%
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* deviation from the nominal frequency. All other rates require a precision
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* of 2000 ppm and thus a crystal!
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* Default if not specified: 12 MHz
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*/
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/* ----------------------- Optional Hardware Config ------------------------ */
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/* #define USB_CFG_PULLUP_IOPORTNAME D */
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/* If you connect the 1.5k pullup resistor from D- to a port pin instead of
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* V+, you can connect and disconnect the device from firmware by calling
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* the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h).
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* This constant defines the port on which the pullup resistor is connected.
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*/
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/* #define USB_CFG_PULLUP_BIT 4 */
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/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined
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* above) where the 1.5k pullup resistor is connected. See description
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* above for details.
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*/
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/* --------------------------- Functional Range ---------------------------- */
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#define USB_CFG_HAVE_INTRIN_ENDPOINT 1
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/* Define this to 1 if you want to compile a version with two endpoints: The
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* default control endpoint 0 and an interrupt-in endpoint 1.
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*/
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#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0
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/* Define this to 1 if you want to compile a version with three endpoints: The
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* default control endpoint 0, an interrupt-in endpoint 1 and an interrupt-in
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* endpoint 3. You must also enable endpoint 1 above.
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*/
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/* #define USB_INITIAL_DATATOKEN USBPID_DATA0 */
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/* The above macro defines the startup condition for data toggling on the
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* interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA0.
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*/
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#define USB_CFG_IMPLEMENT_HALT 0
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/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature
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* for endpoint 1 (interrupt endpoint). Although you may not need this feature,
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* it is required by the standard. We have made it a config option because it
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* bloats the code considerably.
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*/
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#define USB_CFG_INTR_POLL_INTERVAL 20
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/* If you compile a version with endpoint 1 (interrupt-in), this is the poll
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* interval. The value is in milliseconds and must not be less than 10 ms for
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* low speed devices.
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*/
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#define USB_CFG_IS_SELF_POWERED 0
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/* Define this to 1 if the device has its own power supply. Set it to 0 if the
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* device is powered from the USB bus.
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*/
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#define USB_CFG_MAX_BUS_POWER 100
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/* Set this variable to the maximum USB bus power consumption of your device.
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* The value is in milliamperes. [It will be divided by two since USB
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* communicates power requirements in units of 2 mA.]
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||||
*/
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||||
#define USB_CFG_IMPLEMENT_FN_WRITE 0
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/* Set this to 1 if you want usbFunctionWrite() to be called for control-out
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* transfers. Set it to 0 if you don't need it and want to save a couple of
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* bytes.
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*/
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#define USB_CFG_IMPLEMENT_FN_READ 0
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/* Set this to 1 if you need to send control replies which are generated
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* "on the fly" when usbFunctionRead() is called. If you only want to send
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* data from a static buffer, set it to 0 and return the data from
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* usbFunctionSetup(). This saves a couple of bytes.
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*/
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#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0
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/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoint 1.
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* You must implement the function usbFunctionWriteOut() which receives all
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* interrupt/bulk data sent to endpoint 1.
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*/
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#define USB_CFG_HAVE_FLOWCONTROL 0
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/* Define this to 1 if you want flowcontrol over USB data. See the definition
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* of the macros usbDisableAllRequests() and usbEnableAllRequests() in
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* usbdrv.h.
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*/
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/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */
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/* This macro is a hook if you want to do unconventional things. If it is
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* defined, it's inserted at the beginning of received message processing.
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* If you eat the received message and don't want default processing to
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* proceed, do a return after doing your things. One possible application
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* (besides debugging) is to flash a status LED on each packet.
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*/
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#define USB_COUNT_SOF 0
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/* define this macro to 1 if you need the global variable "usbSofCount" which
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* counts SOF packets.
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*/
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/* -------------------------- Device Description --------------------------- */
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#define USB_CFG_VENDOR_ID 0xc0, 0x16
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/* USB vendor ID for the device, low byte first. If you have registered your
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* own Vendor ID, define it here. Otherwise you use obdev's free shared
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* VID/PID pair. Be sure to read USBID-License.txt for rules!
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* This template uses obdev's shared VID/PID pair for HIDs: 0x16c0/0x5df.
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* Use this VID/PID pair ONLY if you understand the implications!
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*/
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#define USB_CFG_DEVICE_ID 0xdf, 0x05
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/* This is the ID of the product, low byte first. It is interpreted in the
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* scope of the vendor ID. If you have registered your own VID with usb.org
|
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* or if you have licensed a PID from somebody else, define it here. Otherwise
|
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* you use obdev's free shared VID/PID pair. Be sure to read the rules in
|
||||
* USBID-License.txt!
|
||||
* This template uses obdev's shared VID/PID pair for HIDs: 0x16c0/0x5df.
|
||||
* Use this VID/PID pair ONLY if you understand the implications!
|
||||
*/
|
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#define USB_CFG_DEVICE_VERSION 0x00, 0x01
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/* Version number of the device: Minor number first, then major number.
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*/
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#define USB_CFG_VENDOR_NAME 'w', 'w', 'w', '.', 'o', 'b', 'd', 'e', 'v', '.', 'a', 't'
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#define USB_CFG_VENDOR_NAME_LEN 12
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/* These two values define the vendor name returned by the USB device. The name
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* must be given as a list of characters under single quotes. The characters
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* are interpreted as Unicode (UTF-16) entities.
|
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* If you don't want a vendor name string, undefine these macros.
|
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* ALWAYS define a vendor name containing your Internet domain name if you use
|
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* obdev's free shared VID/PID pair. See the file USBID-License.txt for
|
||||
* details.
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*/
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#define USB_CFG_DEVICE_NAME 'T', 'e', 'm', 'p', 'l', 'a', 't', 'e'
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#define USB_CFG_DEVICE_NAME_LEN 8
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||||
/* Same as above for the device name. If you don't want a device name, undefine
|
||||
* the macros. See the file USBID-License.txt before you assign a name if you
|
||||
* use a shared VID/PID.
|
||||
*/
|
||||
/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */
|
||||
/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */
|
||||
/* Same as above for the serial number. If you don't want a serial number,
|
||||
* undefine the macros.
|
||||
* It may be useful to provide the serial number through other means than at
|
||||
* compile time. See the section about descriptor properties below for how
|
||||
* to fine tune control over USB descriptors such as the string descriptor
|
||||
* for the serial number.
|
||||
*/
|
||||
#define USB_CFG_DEVICE_CLASS 0
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||||
#define USB_CFG_DEVICE_SUBCLASS 0
|
||||
/* See USB specification if you want to conform to an existing device class.
|
||||
*/
|
||||
#define USB_CFG_INTERFACE_CLASS 3 /* HID */
|
||||
#define USB_CFG_INTERFACE_SUBCLASS 0
|
||||
#define USB_CFG_INTERFACE_PROTOCOL 0
|
||||
/* See USB specification if you want to conform to an existing device class or
|
||||
* protocol.
|
||||
* This template defines a HID class device. If you implement a vendor class
|
||||
* device, set USB_CFG_INTERFACE_CLASS to 0 and USB_CFG_DEVICE_CLASS to 0xff.
|
||||
*/
|
||||
#define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 /* total length of report descriptor */
|
||||
/* Define this to the length of the HID report descriptor, if you implement
|
||||
* an HID device. Otherwise don't define it or define it to 0.
|
||||
* Since this template defines a HID device, it must also specify a HID
|
||||
* report descriptor length. You must add a PROGMEM character array named
|
||||
* "usbHidReportDescriptor" to your code which contains the report descriptor.
|
||||
* Don't forget to keep the array and this define in sync!
|
||||
*/
|
||||
|
||||
/* #define USB_PUBLIC static */
|
||||
/* Use the define above if you #include usbdrv.c instead of linking against it.
|
||||
* This technique saves a couple of bytes in flash memory.
|
||||
*/
|
||||
|
||||
/* ------------------- Fine Control over USB Descriptors ------------------- */
|
||||
/* If you don't want to use the driver's default USB descriptors, you can
|
||||
* provide our own. These can be provided as (1) fixed length static data in
|
||||
* flash memory, (2) fixed length static data in RAM or (3) dynamically at
|
||||
* runtime in the function usbFunctionDescriptor(). See usbdrv.h for more
|
||||
* information about this function.
|
||||
* Descriptor handling is configured through the descriptor's properties. If
|
||||
* no properties are defined or if they are 0, the default descriptor is used.
|
||||
* Possible properties are:
|
||||
* + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched
|
||||
* at runtime via usbFunctionDescriptor().
|
||||
* + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found
|
||||
* in static memory is in RAM, not in flash memory.
|
||||
* + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash),
|
||||
* the driver must know the descriptor's length. The descriptor itself is
|
||||
* found at the address of a well known identifier (see below).
|
||||
* List of static descriptor names (must be declared PROGMEM if in flash):
|
||||
* char usbDescriptorDevice[];
|
||||
* char usbDescriptorConfiguration[];
|
||||
* char usbDescriptorHidReport[];
|
||||
* char usbDescriptorString0[];
|
||||
* int usbDescriptorStringVendor[];
|
||||
* int usbDescriptorStringDevice[];
|
||||
* int usbDescriptorStringSerialNumber[];
|
||||
* Other descriptors can't be provided statically, they must be provided
|
||||
* dynamically at runtime.
|
||||
*
|
||||
* Descriptor properties are or-ed or added together, e.g.:
|
||||
* #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18))
|
||||
*
|
||||
* The following descriptors are defined:
|
||||
* USB_CFG_DESCR_PROPS_DEVICE
|
||||
* USB_CFG_DESCR_PROPS_CONFIGURATION
|
||||
* USB_CFG_DESCR_PROPS_STRINGS
|
||||
* USB_CFG_DESCR_PROPS_STRING_0
|
||||
* USB_CFG_DESCR_PROPS_STRING_VENDOR
|
||||
* USB_CFG_DESCR_PROPS_STRING_PRODUCT
|
||||
* USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER
|
||||
* USB_CFG_DESCR_PROPS_HID
|
||||
* USB_CFG_DESCR_PROPS_HID_REPORT
|
||||
* USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver)
|
||||
*
|
||||
*/
|
||||
|
||||
#define USB_CFG_DESCR_PROPS_DEVICE 0
|
||||
#define USB_CFG_DESCR_PROPS_CONFIGURATION 0
|
||||
#define USB_CFG_DESCR_PROPS_STRINGS 0
|
||||
#define USB_CFG_DESCR_PROPS_STRING_0 0
|
||||
#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0
|
||||
#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0
|
||||
#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0
|
||||
#define USB_CFG_DESCR_PROPS_HID 0
|
||||
#define USB_CFG_DESCR_PROPS_HID_REPORT 0
|
||||
#define USB_CFG_DESCR_PROPS_UNKNOWN 0
|
||||
|
||||
/* ----------------------- Optional MCU Description ------------------------ */
|
||||
|
||||
/* The following configurations have working defaults in usbdrv.h. You
|
||||
* usually don't need to set them explicitly. Only if you want to run
|
||||
* the driver on a device which is not yet supported or with a compiler
|
||||
* which is not fully supported (such as IAR C) or if you use a differnt
|
||||
* interrupt than INT0, you may have to define some of these.
|
||||
*/
|
||||
/* #define USB_INTR_CFG MCUCR */
|
||||
/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */
|
||||
/* #define USB_INTR_CFG_CLR 0 */
|
||||
/* #define USB_INTR_ENABLE GIMSK */
|
||||
/* #define USB_INTR_ENABLE_BIT INT0 */
|
||||
/* #define USB_INTR_PENDING GIFR */
|
||||
/* #define USB_INTR_PENDING_BIT INTF0 */
|
||||
/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */
|
||||
|
||||
#endif /* __usbconfig_h_included__ */
|
||||
|
|
@ -0,0 +1,561 @@
|
|||
/* Name: usbdrvasm12.S
|
||||
* Project: AVR USB driver
|
||||
* Author: Christian Starkjohann
|
||||
* Creation Date: 2004-12-29
|
||||
* Tabsize: 4
|
||||
* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
|
||||
* License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
|
||||
* This Revision: $Id: usbdrvasm12.S,v 1.1 2013-04-25 02:18:15 cvs Exp $
|
||||
*/
|
||||
|
||||
/* Do not link this file! Link usbdrvasm.S instead, which includes the
|
||||
* appropriate implementation!
|
||||
*/
|
||||
|
||||
/*
|
||||
General Description:
|
||||
This file is the 12 MHz version of the asssembler part of the USB driver. It
|
||||
requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
|
||||
oscillator).
|
||||
|
||||
See usbdrv.h for a description of the entire driver.
|
||||
|
||||
Since almost all of this code is timing critical, don't change unless you
|
||||
really know what you are doing! Many parts require not only a maximum number
|
||||
of CPU cycles, but even an exact number of cycles!
|
||||
|
||||
|
||||
Timing constraints according to spec (in bit times):
|
||||
timing subject min max CPUcycles
|
||||
---------------------------------------------------------------------------
|
||||
EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
|
||||
EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
|
||||
DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
|
||||
*/
|
||||
|
||||
;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
|
||||
;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
|
||||
;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
|
||||
;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
|
||||
;Numbers in brackets are maximum cycles since SOF.
|
||||
USB_INTR_VECTOR:
|
||||
;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
|
||||
push YL ;2 [35] push only what is necessary to sync with edge ASAP
|
||||
in YL, SREG ;1 [37]
|
||||
push YL ;2 [39]
|
||||
;----------------------------------------------------------------------------
|
||||
; Synchronize with sync pattern:
|
||||
;----------------------------------------------------------------------------
|
||||
;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
|
||||
;sync up with J to K edge during sync pattern -- use fastest possible loops
|
||||
;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
|
||||
waitForJ:
|
||||
sbis USBIN, USBMINUS ;1 [40] wait for D- == 1
|
||||
rjmp waitForJ ;2
|
||||
waitForK:
|
||||
;The following code results in a sampling window of 1/4 bit which meets the spec.
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
#if USB_COUNT_SOF
|
||||
lds YL, usbSofCount
|
||||
inc YL
|
||||
sts usbSofCount, YL
|
||||
#endif /* USB_COUNT_SOF */
|
||||
rjmp sofError
|
||||
foundK:
|
||||
;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
|
||||
;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
|
||||
;are cycles from center of first sync (double K) bit after the instruction
|
||||
push YH ;2 [2]
|
||||
lds YL, usbInputBufOffset;2 [4]
|
||||
clr YH ;1 [5]
|
||||
subi YL, lo8(-(usbRxBuf));1 [6]
|
||||
sbci YH, hi8(-(usbRxBuf));1 [7]
|
||||
|
||||
sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
|
||||
rjmp haveTwoBitsK ;2 [10]
|
||||
pop YH ;2 [11] undo the push from before
|
||||
rjmp waitForK ;2 [13] this was not the end of sync, retry
|
||||
haveTwoBitsK:
|
||||
;----------------------------------------------------------------------------
|
||||
; push more registers and initialize values while we sample the first bits:
|
||||
;----------------------------------------------------------------------------
|
||||
push shift ;2 [16]
|
||||
push x1 ;2 [12]
|
||||
push x2 ;2 [14]
|
||||
|
||||
in x1, USBIN ;1 [17] <-- sample bit 0
|
||||
ldi shift, 0xff ;1 [18]
|
||||
bst x1, USBMINUS ;1 [19]
|
||||
bld shift, 0 ;1 [20]
|
||||
push x3 ;2 [22]
|
||||
push cnt ;2 [24]
|
||||
|
||||
in x2, USBIN ;1 [25] <-- sample bit 1
|
||||
ser x3 ;1 [26] [inserted init instruction]
|
||||
eor x1, x2 ;1 [27]
|
||||
bst x1, USBMINUS ;1 [28]
|
||||
bld shift, 1 ;1 [29]
|
||||
ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
|
||||
rjmp rxbit2 ;2 [32]
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; Receiver loop (numbers in brackets are cycles within byte after instr)
|
||||
;----------------------------------------------------------------------------
|
||||
|
||||
unstuff0: ;1 (branch taken)
|
||||
andi x3, ~0x01 ;1 [15]
|
||||
mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
|
||||
in x2, USBIN ;1 [17] <-- sample bit 1 again
|
||||
ori shift, 0x01 ;1 [18]
|
||||
rjmp didUnstuff0 ;2 [20]
|
||||
|
||||
unstuff1: ;1 (branch taken)
|
||||
mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
|
||||
andi x3, ~0x02 ;1 [22]
|
||||
ori shift, 0x02 ;1 [23]
|
||||
nop ;1 [24]
|
||||
in x1, USBIN ;1 [25] <-- sample bit 2 again
|
||||
rjmp didUnstuff1 ;2 [27]
|
||||
|
||||
unstuff2: ;1 (branch taken)
|
||||
andi x3, ~0x04 ;1 [29]
|
||||
ori shift, 0x04 ;1 [30]
|
||||
mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
|
||||
nop ;1 [32]
|
||||
in x2, USBIN ;1 [33] <-- sample bit 3
|
||||
rjmp didUnstuff2 ;2 [35]
|
||||
|
||||
unstuff3: ;1 (branch taken)
|
||||
in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
|
||||
andi x3, ~0x08 ;1 [35]
|
||||
ori shift, 0x08 ;1 [36]
|
||||
rjmp didUnstuff3 ;2 [38]
|
||||
|
||||
unstuff4: ;1 (branch taken)
|
||||
andi x3, ~0x10 ;1 [40]
|
||||
in x1, USBIN ;1 [41] <-- sample stuffed bit 4
|
||||
ori shift, 0x10 ;1 [42]
|
||||
rjmp didUnstuff4 ;2 [44]
|
||||
|
||||
unstuff5: ;1 (branch taken)
|
||||
andi x3, ~0x20 ;1 [48]
|
||||
in x2, USBIN ;1 [49] <-- sample stuffed bit 5
|
||||
ori shift, 0x20 ;1 [50]
|
||||
rjmp didUnstuff5 ;2 [52]
|
||||
|
||||
unstuff6: ;1 (branch taken)
|
||||
andi x3, ~0x40 ;1 [56]
|
||||
in x1, USBIN ;1 [57] <-- sample stuffed bit 6
|
||||
ori shift, 0x40 ;1 [58]
|
||||
rjmp didUnstuff6 ;2 [60]
|
||||
|
||||
; extra jobs done during bit interval:
|
||||
; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
|
||||
; bit 1: se0 check
|
||||
; bit 2: overflow check
|
||||
; bit 3: recovery from delay [bit 0 tasks took too long]
|
||||
; bit 4: none
|
||||
; bit 5: none
|
||||
; bit 6: none
|
||||
; bit 7: jump, eor
|
||||
rxLoop:
|
||||
eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
|
||||
in x1, USBIN ;1 [1] <-- sample bit 0
|
||||
st y+, x3 ;2 [3] store data
|
||||
ser x3 ;1 [4]
|
||||
nop ;1 [5]
|
||||
eor x2, x1 ;1 [6]
|
||||
bst x2, USBMINUS;1 [7]
|
||||
bld shift, 0 ;1 [8]
|
||||
in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
|
||||
andi x2, USBMASK ;1 [10]
|
||||
breq se0 ;1 [11] SE0 check for bit 1
|
||||
andi shift, 0xf9 ;1 [12]
|
||||
didUnstuff0:
|
||||
breq unstuff0 ;1 [13]
|
||||
eor x1, x2 ;1 [14]
|
||||
bst x1, USBMINUS;1 [15]
|
||||
bld shift, 1 ;1 [16]
|
||||
rxbit2:
|
||||
in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
|
||||
andi shift, 0xf3 ;1 [18]
|
||||
breq unstuff1 ;1 [19] do remaining work for bit 1
|
||||
didUnstuff1:
|
||||
subi cnt, 1 ;1 [20]
|
||||
brcs overflow ;1 [21] loop control
|
||||
eor x2, x1 ;1 [22]
|
||||
bst x2, USBMINUS;1 [23]
|
||||
bld shift, 2 ;1 [24]
|
||||
in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
|
||||
andi shift, 0xe7 ;1 [26]
|
||||
breq unstuff2 ;1 [27]
|
||||
didUnstuff2:
|
||||
eor x1, x2 ;1 [28]
|
||||
bst x1, USBMINUS;1 [29]
|
||||
bld shift, 3 ;1 [30]
|
||||
didUnstuff3:
|
||||
andi shift, 0xcf ;1 [31]
|
||||
breq unstuff3 ;1 [32]
|
||||
in x1, USBIN ;1 [33] <-- sample bit 4
|
||||
eor x2, x1 ;1 [34]
|
||||
bst x2, USBMINUS;1 [35]
|
||||
bld shift, 4 ;1 [36]
|
||||
didUnstuff4:
|
||||
andi shift, 0x9f ;1 [37]
|
||||
breq unstuff4 ;1 [38]
|
||||
nop2 ;2 [40]
|
||||
in x2, USBIN ;1 [41] <-- sample bit 5
|
||||
eor x1, x2 ;1 [42]
|
||||
bst x1, USBMINUS;1 [43]
|
||||
bld shift, 5 ;1 [44]
|
||||
didUnstuff5:
|
||||
andi shift, 0x3f ;1 [45]
|
||||
breq unstuff5 ;1 [46]
|
||||
nop2 ;2 [48]
|
||||
in x1, USBIN ;1 [49] <-- sample bit 6
|
||||
eor x2, x1 ;1 [50]
|
||||
bst x2, USBMINUS;1 [51]
|
||||
bld shift, 6 ;1 [52]
|
||||
didUnstuff6:
|
||||
cpi shift, 0x02 ;1 [53]
|
||||
brlo unstuff6 ;1 [54]
|
||||
nop2 ;2 [56]
|
||||
in x2, USBIN ;1 [57] <-- sample bit 7
|
||||
eor x1, x2 ;1 [58]
|
||||
bst x1, USBMINUS;1 [59]
|
||||
bld shift, 7 ;1 [60]
|
||||
didUnstuff7:
|
||||
cpi shift, 0x04 ;1 [61]
|
||||
brsh rxLoop ;2 [63] loop control
|
||||
unstuff7:
|
||||
andi x3, ~0x80 ;1 [63]
|
||||
ori shift, 0x80 ;1 [64]
|
||||
in x2, USBIN ;1 [65] <-- sample stuffed bit 7
|
||||
nop ;1 [66]
|
||||
rjmp didUnstuff7 ;2 [68]
|
||||
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; Processing of received packet (numbers in brackets are cycles after end of SE0)
|
||||
;----------------------------------------------------------------------------
|
||||
;This is the only non-error exit point for the software receiver loop
|
||||
;we don't check any CRCs here because there is no time left.
|
||||
#define token x1
|
||||
se0: ; [0]
|
||||
subi cnt, USB_BUFSIZE ;1 [1]
|
||||
neg cnt ;1 [2]
|
||||
cpi cnt, 3 ;1 [3]
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [4]
|
||||
USB_STORE_PENDING(x2) ;1 [5] clear pending intr and check flag later. SE0 should be over.
|
||||
brlo doReturn ;1 [6] this is probably an ACK, NAK or similar packet
|
||||
sub YL, cnt ;1 [7]
|
||||
sbci YH, 0 ;1 [8]
|
||||
ld token, y ;2 [10]
|
||||
cpi token, USBPID_DATA0 ;1 [11]
|
||||
breq handleData ;1 [12]
|
||||
cpi token, USBPID_DATA1 ;1 [13]
|
||||
breq handleData ;1 [14]
|
||||
ldd x2, y+1 ;2 [16] ADDR and 1 bit endpoint number
|
||||
mov x3, x2 ;1 [17] store for endpoint number
|
||||
andi x2, 0x7f ;1 [18] x2 is now ADDR
|
||||
lds shift, usbDeviceAddr;2 [20]
|
||||
cp x2, shift ;1 [21]
|
||||
overflow: ; This is a hack: brcs overflow will never have Z flag set
|
||||
brne ignorePacket ;1 [22] packet for different address
|
||||
cpi token, USBPID_IN ;1 [23]
|
||||
breq handleIn ;1 [24]
|
||||
cpi token, USBPID_SETUP ;1 [25]
|
||||
breq handleSetupOrOut ;1 [26]
|
||||
cpi token, USBPID_OUT ;1 [27]
|
||||
breq handleSetupOrOut ;1 [28]
|
||||
; rjmp ignorePacket ;fallthrough, should not happen anyway.
|
||||
|
||||
ignorePacket:
|
||||
clr shift
|
||||
sts usbCurrentTok, shift
|
||||
doReturn:
|
||||
pop cnt
|
||||
pop x3
|
||||
pop x2
|
||||
pop x1
|
||||
pop shift
|
||||
pop YH
|
||||
sofError:
|
||||
pop YL
|
||||
out SREG, YL
|
||||
pop YL
|
||||
reti
|
||||
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
handleIn3: ;1 [38] (branch taken)
|
||||
lds cnt, usbTxLen3 ;2 [40]
|
||||
sbrc cnt, 4 ;2 [42]
|
||||
rjmp sendCntAndReti ;0 43 + 17 = 60 until SOP
|
||||
sts usbTxLen3, x1 ;2 [44] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf3) ;1 [45]
|
||||
ldi YH, hi8(usbTxBuf3) ;1 [46]
|
||||
rjmp usbSendAndReti ;2 [48] + 13 = 61 until SOP (violates the spec by 1 cycle)
|
||||
#endif
|
||||
|
||||
;Setup and Out are followed by a data packet two bit times (16 cycles) after
|
||||
;the end of SE0. The sync code allows up to 40 cycles delay from the start of
|
||||
;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
|
||||
handleSetupOrOut: ;1 [29] (branch taken)
|
||||
#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
|
||||
sbrc x3, 7 ;1 [30] skip if endpoint 0
|
||||
ldi token, -1 ;1 [31] indicate that this is endpoint 1 OUT
|
||||
#endif
|
||||
sts usbCurrentTok, token;2 [33]
|
||||
pop cnt ;2 [35]
|
||||
pop x3 ;2 [37]
|
||||
pop x2 ;2 [39]
|
||||
pop x1 ;2 [41]
|
||||
pop shift ;2 [43]
|
||||
pop YH ;2 [45]
|
||||
USB_LOAD_PENDING(YL) ;1 [46]
|
||||
sbrc YL, USB_INTR_PENDING_BIT;1 [47] check whether data is already arriving
|
||||
rjmp waitForJ ;2 [49] save the pops and pushes -- a new interrupt is aready pending
|
||||
rjmp sofError ;2 not an error, but it does the pops and reti we want
|
||||
|
||||
|
||||
handleData: ;1 [15] (branch taken)
|
||||
lds token, usbCurrentTok;2 [17]
|
||||
tst token ;1 [18]
|
||||
breq doReturn ;1 [19]
|
||||
lds x2, usbRxLen ;2 [21]
|
||||
tst x2 ;1 [22]
|
||||
brne sendNakAndReti ;1 [23]
|
||||
; 2006-03-11: The following two lines fix a problem where the device was not
|
||||
; recognized if usbPoll() was called less frequently than once every 4 ms.
|
||||
cpi cnt, 4 ;1 [24] zero sized data packets are status phase only -- ignore and ack
|
||||
brmi sendAckAndReti ;1 [25] keep rx buffer clean -- we must not NAK next SETUP
|
||||
sts usbRxLen, cnt ;2 [27] store received data, swap buffers
|
||||
sts usbRxToken, token ;2 [29]
|
||||
lds x2, usbInputBufOffset;2 [31] swap buffers
|
||||
ldi cnt, USB_BUFSIZE ;1 [32]
|
||||
sub cnt, x2 ;1 [33]
|
||||
sts usbInputBufOffset, cnt;2 [35] buffers now swapped
|
||||
rjmp sendAckAndReti ;2 [37] + 19 = 56 until SOP
|
||||
|
||||
handleIn: ;1 [25] (branch taken)
|
||||
;We don't send any data as long as the C code has not processed the current
|
||||
;input data and potentially updated the output data. That's more efficient
|
||||
;in terms of code size than clearing the tx buffers when a packet is received.
|
||||
lds x1, usbRxLen ;2 [27]
|
||||
cpi x1, 1 ;1 [28] negative values are flow control, 0 means "buffer free"
|
||||
brge sendNakAndReti ;1 [29] unprocessed input packet?
|
||||
ldi x1, USBPID_NAK ;1 [30] prepare value for usbTxLen
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT
|
||||
sbrc x3, 7 ;2 [33] x3 contains addr + endpoint
|
||||
rjmp handleIn1 ;0
|
||||
#endif
|
||||
lds cnt, usbTxLen ;2 [34]
|
||||
sbrc cnt, 4 ;2 [36] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;0 37 + 17 = 54 until SOP
|
||||
sts usbTxLen, x1 ;2 [38] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf) ;1 [39]
|
||||
ldi YH, hi8(usbTxBuf) ;1 [40]
|
||||
rjmp usbSendAndReti ;2 [42] + 14 = 56 until SOP
|
||||
|
||||
; Comment about when to set usbTxLen to USBPID_NAK:
|
||||
; We should set it back when we receive the ACK from the host. This would
|
||||
; be simple to implement: One static variable which stores whether the last
|
||||
; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
|
||||
; ACK. However, we set it back immediately when we send the package,
|
||||
; assuming that no error occurs and the host sends an ACK. We save one byte
|
||||
; RAM this way and avoid potential problems with endless retries. The rest of
|
||||
; the driver assumes error-free transfers anyway.
|
||||
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
|
||||
handleIn1: ;1 [33] (branch taken)
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
|
||||
ldd x2, y+2 ;2 [35]
|
||||
sbrc x2, 0 ;2 [37]
|
||||
rjmp handleIn3 ;0
|
||||
#endif
|
||||
lds cnt, usbTxLen1 ;2 [39]
|
||||
sbrc cnt, 4 ;2 [41] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;0 42 + 17 = 59 until SOP
|
||||
sts usbTxLen1, x1 ;2 [43] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf1) ;1 [44]
|
||||
ldi YH, hi8(usbTxBuf1) ;1 [45]
|
||||
rjmp usbSendAndReti ;2 [47] + 13 = 60 until SOP
|
||||
#endif
|
||||
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; Transmitting data
|
||||
;----------------------------------------------------------------------------
|
||||
|
||||
bitstuff0: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
ldi x2, 0 ;1
|
||||
out USBOUT, x1 ;1 <-- out
|
||||
rjmp didStuff0 ;2 branch back 2 cycles earlier
|
||||
bitstuff1: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
rjmp didStuff1 ;2 we know that C is clear, jump back to do OUT and ror 0 into x2
|
||||
bitstuff2: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
rjmp didStuff2 ;2 jump back 4 cycles earlier and do out and ror 0 into x2
|
||||
bitstuff3: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
rjmp didStuff3 ;2 jump back earlier and ror 0 into x2
|
||||
bitstuff4: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
ldi x2, 0 ;1
|
||||
out USBOUT, x1 ;1 <-- out
|
||||
rjmp didStuff4 ;2 jump back 2 cycles earlier
|
||||
|
||||
sendNakAndReti: ;0 [-19] 19 cycles until SOP
|
||||
ldi x3, USBPID_NAK ;1 [-18]
|
||||
rjmp usbSendX3 ;2 [-16]
|
||||
sendAckAndReti: ;0 [-19] 19 cycles until SOP
|
||||
ldi x3, USBPID_ACK ;1 [-18]
|
||||
rjmp usbSendX3 ;2 [-16]
|
||||
sendCntAndReti: ;0 [-17] 17 cycles until SOP
|
||||
mov x3, cnt ;1 [-16]
|
||||
usbSendX3: ;0 [-16]
|
||||
ldi YL, 20 ;1 [-15] 'x3' is R20
|
||||
ldi YH, 0 ;1 [-14]
|
||||
ldi cnt, 2 ;1 [-13]
|
||||
; rjmp usbSendAndReti fallthrough
|
||||
|
||||
; USB spec says:
|
||||
; idle = J
|
||||
; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
|
||||
; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
|
||||
; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
|
||||
|
||||
;usbSend:
|
||||
;pointer to data in 'Y'
|
||||
;number of bytes in 'cnt' -- including sync byte
|
||||
;uses: x1...x4, shift, cnt, Y
|
||||
;Numbers in brackets are time since first bit of sync pattern is sent
|
||||
usbSendAndReti: ;0 [-13] timing: 13 cycles until SOP
|
||||
in x2, USBDDR ;1 [-12]
|
||||
ori x2, USBMASK ;1 [-11]
|
||||
sbi USBOUT, USBMINUS;2 [-9] prepare idle state; D+ and D- must have been 0 (no pullups)
|
||||
in x1, USBOUT ;1 [-8] port mirror for tx loop
|
||||
out USBDDR, x2 ;1 [-7] <- acquire bus
|
||||
; need not init x2 (bitstuff history) because sync starts with 0
|
||||
push x4 ;2 [-5]
|
||||
ldi x4, USBMASK ;1 [-4] exor mask
|
||||
ldi shift, 0x80 ;1 [-3] sync byte is first byte sent
|
||||
txLoop: ; [62]
|
||||
sbrs shift, 0 ;1 [-2] [62]
|
||||
eor x1, x4 ;1 [-1] [63]
|
||||
out USBOUT, x1 ;1 [0] <-- out bit 0
|
||||
ror shift ;1 [1]
|
||||
ror x2 ;1 [2]
|
||||
didStuff0:
|
||||
cpi x2, 0xfc ;1 [3]
|
||||
brsh bitstuff0 ;1 [4]
|
||||
sbrs shift, 0 ;1 [5]
|
||||
eor x1, x4 ;1 [6]
|
||||
ror shift ;1 [7]
|
||||
didStuff1:
|
||||
out USBOUT, x1 ;1 [8] <-- out bit 1
|
||||
ror x2 ;1 [9]
|
||||
cpi x2, 0xfc ;1 [10]
|
||||
brsh bitstuff1 ;1 [11]
|
||||
sbrs shift, 0 ;1 [12]
|
||||
eor x1, x4 ;1 [13]
|
||||
ror shift ;1 [14]
|
||||
didStuff2:
|
||||
ror x2 ;1 [15]
|
||||
out USBOUT, x1 ;1 [16] <-- out bit 2
|
||||
cpi x2, 0xfc ;1 [17]
|
||||
brsh bitstuff2 ;1 [18]
|
||||
sbrs shift, 0 ;1 [19]
|
||||
eor x1, x4 ;1 [20]
|
||||
ror shift ;1 [21]
|
||||
didStuff3:
|
||||
ror x2 ;1 [22]
|
||||
cpi x2, 0xfc ;1 [23]
|
||||
out USBOUT, x1 ;1 [24] <-- out bit 3
|
||||
brsh bitstuff3 ;1 [25]
|
||||
nop2 ;2 [27]
|
||||
ld x3, y+ ;2 [29]
|
||||
sbrs shift, 0 ;1 [30]
|
||||
eor x1, x4 ;1 [31]
|
||||
out USBOUT, x1 ;1 [32] <-- out bit 4
|
||||
ror shift ;1 [33]
|
||||
ror x2 ;1 [34]
|
||||
didStuff4:
|
||||
cpi x2, 0xfc ;1 [35]
|
||||
brsh bitstuff4 ;1 [36]
|
||||
sbrs shift, 0 ;1 [37]
|
||||
eor x1, x4 ;1 [38]
|
||||
ror shift ;1 [39]
|
||||
didStuff5:
|
||||
out USBOUT, x1 ;1 [40] <-- out bit 5
|
||||
ror x2 ;1 [41]
|
||||
cpi x2, 0xfc ;1 [42]
|
||||
brsh bitstuff5 ;1 [43]
|
||||
sbrs shift, 0 ;1 [44]
|
||||
eor x1, x4 ;1 [45]
|
||||
ror shift ;1 [46]
|
||||
didStuff6:
|
||||
ror x2 ;1 [47]
|
||||
out USBOUT, x1 ;1 [48] <-- out bit 6
|
||||
cpi x2, 0xfc ;1 [49]
|
||||
brsh bitstuff6 ;1 [50]
|
||||
sbrs shift, 0 ;1 [51]
|
||||
eor x1, x4 ;1 [52]
|
||||
ror shift ;1 [53]
|
||||
didStuff7:
|
||||
ror x2 ;1 [54]
|
||||
cpi x2, 0xfc ;1 [55]
|
||||
out USBOUT, x1 ;1 [56] <-- out bit 7
|
||||
brsh bitstuff7 ;1 [57]
|
||||
mov shift, x3 ;1 [58]
|
||||
dec cnt ;1 [59]
|
||||
brne txLoop ;1/2 [60/61]
|
||||
;make SE0:
|
||||
cbr x1, USBMASK ;1 [61] prepare SE0 [spec says EOP may be 15 to 18 cycles]
|
||||
pop x4 ;2 [63]
|
||||
;brackets are cycles from start of SE0 now
|
||||
out USBOUT, x1 ;1 [0] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
|
||||
nop2 ;2 [2]
|
||||
;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
||||
;set address only after data packet was sent, not after handshake
|
||||
lds x2, usbNewDeviceAddr;2 [4]
|
||||
subi YL, 20 + 2 ;1 [5]
|
||||
sbci YH, 0 ;1 [6]
|
||||
breq skipAddrAssign ;2 [8]
|
||||
sts usbDeviceAddr, x2;0 if not skipped: SE0 is one cycle longer
|
||||
skipAddrAssign:
|
||||
;end of usbDeviceAddress transfer
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT;1 [9] int0 occurred during TX -- clear pending flag
|
||||
USB_STORE_PENDING(x2) ;1 [10]
|
||||
ori x1, USBIDLE ;1 [11]
|
||||
in x2, USBDDR ;1 [12]
|
||||
cbr x2, USBMASK ;1 [13] set both pins to input
|
||||
mov x3, x1 ;1 [14]
|
||||
cbr x3, USBMASK ;1 [15] configure no pullup on both pins
|
||||
out USBOUT, x1 ;1 [16] <-- out J (idle) -- end of SE0 (EOP signal)
|
||||
out USBDDR, x2 ;1 [17] <-- release bus now
|
||||
out USBOUT, x3 ;1 [18] <-- ensure no pull-up resistors are active
|
||||
rjmp doReturn
|
||||
|
||||
bitstuff5: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
rjmp didStuff5 ;2 same trick as above...
|
||||
bitstuff6: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
rjmp didStuff6 ;2 same trick as above...
|
||||
bitstuff7: ;1 (for branch taken)
|
||||
eor x1, x4 ;1
|
||||
rjmp didStuff7 ;2 same trick as above...
|
||||
|
||||
|
|
@ -0,0 +1,547 @@
|
|||
/* Name: usbdrvasm15.S
|
||||
* Project: AVR USB driver
|
||||
* Author: contributed by V. Bosch
|
||||
* Creation Date: 2007-08-06
|
||||
* Tabsize: 4
|
||||
* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
|
||||
* License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
|
||||
* Revision: $Id: usbdrvasm15.S,v 1.1 2013-04-25 02:18:15 cvs Exp $
|
||||
*/
|
||||
|
||||
|
||||
/* Do not link this file! Link usbdrvasm.S instead, which includes the
|
||||
* appropriate implementation!
|
||||
*/
|
||||
|
||||
/*
|
||||
General Description:
|
||||
This file is the 15 MHz version of the asssembler part of the USB driver. It
|
||||
requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC
|
||||
oscillator).
|
||||
|
||||
See usbdrv.h for a description of the entire driver.
|
||||
|
||||
Since almost all of this code is timing critical, don't change unless you
|
||||
really know what you are doing! Many parts require not only a maximum number
|
||||
of CPU cycles, but even an exact number of cycles!
|
||||
*/
|
||||
|
||||
;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
|
||||
;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
|
||||
; Numbers in brackets are clocks counted from center of last sync bit
|
||||
; when instruction starts
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; order of registers pushed:
|
||||
; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
|
||||
;----------------------------------------------------------------------------
|
||||
USB_INTR_VECTOR:
|
||||
push YL ;2 push only what is necessary to sync with edge ASAP
|
||||
in YL, SREG ;1
|
||||
push YL ;2
|
||||
;----------------------------------------------------------------------------
|
||||
; Synchronize with sync pattern:
|
||||
;
|
||||
; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
|
||||
; sync up with J to K edge during sync pattern -- use fastest possible loops
|
||||
; first part has no timeout because it waits for IDLE or SE1 (== disconnected)
|
||||
;-------------------------------------------------------------------------------
|
||||
waitForJ: ;-
|
||||
sbis USBIN, USBMINUS ;1 <-- sample: wait for D- == 1
|
||||
rjmp waitForJ ;2
|
||||
;-------------------------------------------------------------------------------
|
||||
; The following code results in a sampling window of < 1/4 bit
|
||||
; which meets the spec.
|
||||
;-------------------------------------------------------------------------------
|
||||
waitForK: ;-
|
||||
sbis USBIN, USBMINUS ;1 [00] <-- sample
|
||||
rjmp foundK ;2 [01]
|
||||
sbis USBIN, USBMINUS ; <-- sample
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS ; <-- sample
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS ; <-- sample
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS ; <-- sample
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS ; <-- sample
|
||||
rjmp foundK
|
||||
#if USB_COUNT_SOF
|
||||
lds YL, usbSofCount
|
||||
inc YL
|
||||
sts usbSofCount, YL
|
||||
#endif /* USB_COUNT_SOF */
|
||||
rjmp sofError
|
||||
;------------------------------------------------------------------------------
|
||||
; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
|
||||
; center sampling]
|
||||
; we have 1 bit time for setup purposes, then sample again.
|
||||
; Numbers in brackets are cycles from center of first sync (double K)
|
||||
; bit after the instruction
|
||||
;------------------------------------------------------------------------------
|
||||
foundK: ;- [02]
|
||||
lds YL, usbInputBufOffset;2 [03+04] tx loop
|
||||
push YH ;2 [05+06]
|
||||
clr YH ;1 [07]
|
||||
subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
|
||||
sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
|
||||
push shift ;2 [10+11]
|
||||
ser shift ;1 [12]
|
||||
sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
|
||||
rjmp haveTwoBitsK ;2 [00] [14]
|
||||
pop shift ;2 [15+16] undo the push from before
|
||||
pop YH ;2 [17+18] undo the push from before
|
||||
rjmp waitForK ;2 [19+20] this was not the end of sync, retry
|
||||
; The entire loop from waitForK until rjmp waitForK above must not exceed two
|
||||
; bit times (= 20 cycles).
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; push more registers and initialize values while we sample the first bits:
|
||||
;----------------------------------------------------------------------------
|
||||
haveTwoBitsK: ;- [01]
|
||||
push x1 ;2 [02+03]
|
||||
push x2 ;2 [04+05]
|
||||
push x3 ;2 [06+07]
|
||||
push bitcnt ;2 [08+09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample bit 0
|
||||
bst x1, USBMINUS ;1 [01]
|
||||
bld shift, 0 ;1 [02]
|
||||
push cnt ;2 [03+04]
|
||||
ldi cnt, USB_BUFSIZE ;1 [05]
|
||||
push x4 ;2 [06+07] tx loop
|
||||
rjmp rxLoop ;2 [08]
|
||||
;----------------------------------------------------------------------------
|
||||
; Receiver loop (numbers in brackets are cycles within byte after instr)
|
||||
;----------------------------------------------------------------------------
|
||||
unstuff0: ;- [07] (branch taken)
|
||||
andi x3, ~0x01 ;1 [08]
|
||||
mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
|
||||
in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
|
||||
andi x2, USBMASK ;1 [01]
|
||||
breq se0Hop ;1 [02] SE0 check for bit 1
|
||||
ori shift, 0x01 ;1 [03] 0b00000001
|
||||
nop ;1 [04]
|
||||
rjmp didUnstuff0 ;2 [05]
|
||||
;-----------------------------------------------------
|
||||
unstuff1: ;- [05] (branch taken)
|
||||
mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
|
||||
andi x3, ~0x02 ;1 [07]
|
||||
ori shift, 0x02 ;1 [08] 0b00000010
|
||||
nop ;1 [09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
|
||||
andi x1, USBMASK ;1 [01]
|
||||
breq se0Hop ;1 [02] SE0 check for bit 2
|
||||
rjmp didUnstuff1 ;2 [03]
|
||||
;-----------------------------------------------------
|
||||
unstuff2: ;- [05] (branch taken)
|
||||
andi x3, ~0x04 ;1 [06]
|
||||
ori shift, 0x04 ;1 [07] 0b00000100
|
||||
mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
|
||||
nop ;1 [09]
|
||||
in x2, USBIN ;1 [00] [10] <-- sample bit 3
|
||||
andi x2, USBMASK ;1 [01]
|
||||
breq se0Hop ;1 [02] SE0 check for bit 3
|
||||
rjmp didUnstuff2 ;2 [03]
|
||||
;-----------------------------------------------------
|
||||
unstuff3: ;- [00] [10] (branch taken)
|
||||
in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
|
||||
andi x2, USBMASK ;1 [02]
|
||||
breq se0Hop ;1 [03] SE0 check for stuffed bit 3
|
||||
andi x3, ~0x08 ;1 [04]
|
||||
ori shift, 0x08 ;1 [05] 0b00001000
|
||||
rjmp didUnstuff3 ;2 [06]
|
||||
;----------------------------------------------------------------------------
|
||||
; extra jobs done during bit interval:
|
||||
;
|
||||
; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
|
||||
; overflow check, jump to the head of rxLoop
|
||||
; bit 1: SE0 check
|
||||
; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
|
||||
; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
|
||||
; bit 4: SE0 check, none
|
||||
; bit 5: SE0 check, none
|
||||
; bit 6: SE0 check, none
|
||||
; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
|
||||
;----------------------------------------------------------------------------
|
||||
rxLoop: ;- [09]
|
||||
in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
|
||||
andi x2, USBMASK ;1 [01]
|
||||
brne SkipSe0Hop ;1 [02]
|
||||
se0Hop: ;- [02]
|
||||
rjmp se0 ;2 [03] SE0 check for bit 1
|
||||
SkipSe0Hop: ;- [03]
|
||||
ser x3 ;1 [04]
|
||||
andi shift, 0xf9 ;1 [05] 0b11111001
|
||||
breq unstuff0 ;1 [06]
|
||||
didUnstuff0: ;- [06]
|
||||
eor x1, x2 ;1 [07]
|
||||
bst x1, USBMINUS ;1 [08]
|
||||
bld shift, 1 ;1 [09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
|
||||
andi x1, USBMASK ;1 [01]
|
||||
breq se0Hop ;1 [02] SE0 check for bit 2
|
||||
andi shift, 0xf3 ;1 [03] 0b11110011
|
||||
breq unstuff1 ;1 [04] do remaining work for bit 1
|
||||
didUnstuff1: ;- [04]
|
||||
eor x2, x1 ;1 [05]
|
||||
bst x2, USBMINUS ;1 [06]
|
||||
bld shift, 2 ;1 [07]
|
||||
nop2 ;2 [08+09]
|
||||
in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
|
||||
andi x2, USBMASK ;1 [01]
|
||||
breq se0Hop ;1 [02] SE0 check for bit 3
|
||||
andi shift, 0xe7 ;1 [03] 0b11100111
|
||||
breq unstuff2 ;1 [04]
|
||||
didUnstuff2: ;- [04]
|
||||
eor x1, x2 ;1 [05]
|
||||
bst x1, USBMINUS ;1 [06]
|
||||
bld shift, 3 ;1 [07]
|
||||
didUnstuff3: ;- [07]
|
||||
andi shift, 0xcf ;1 [08] 0b11001111
|
||||
breq unstuff3 ;1 [09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample bit 4
|
||||
andi x1, USBMASK ;1 [01]
|
||||
breq se0Hop ;1 [02] SE0 check for bit 4
|
||||
eor x2, x1 ;1 [03]
|
||||
bst x2, USBMINUS ;1 [04]
|
||||
bld shift, 4 ;1 [05]
|
||||
didUnstuff4: ;- [05]
|
||||
andi shift, 0x9f ;1 [06] 0b10011111
|
||||
breq unstuff4 ;1 [07]
|
||||
nop2 ;2 [08+09]
|
||||
in x2, USBIN ;1 [00] [10] <-- sample bit 5
|
||||
andi x2, USBMASK ;1 [01]
|
||||
breq se0 ;1 [02] SE0 check for bit 5
|
||||
eor x1, x2 ;1 [03]
|
||||
bst x1, USBMINUS ;1 [04]
|
||||
bld shift, 5 ;1 [05]
|
||||
didUnstuff5: ;- [05]
|
||||
andi shift, 0x3f ;1 [06] 0b00111111
|
||||
breq unstuff5 ;1 [07]
|
||||
nop2 ;2 [08+09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample bit 6
|
||||
andi x1, USBMASK ;1 [01]
|
||||
breq se0 ;1 [02] SE0 check for bit 6
|
||||
eor x2, x1 ;1 [03]
|
||||
bst x2, USBMINUS ;1 [04]
|
||||
bld shift, 6 ;1 [05]
|
||||
didUnstuff6: ;- [05]
|
||||
cpi shift, 0x02 ;1 [06] 0b00000010
|
||||
brlo unstuff6 ;1 [07]
|
||||
nop2 ;2 [08+09]
|
||||
in x2, USBIN ;1 [00] [10] <-- sample bit 7
|
||||
andi x2, USBMASK ;1 [01]
|
||||
breq se0 ;1 [02] SE0 check for bit 7
|
||||
eor x1, x2 ;1 [03]
|
||||
bst x1, USBMINUS ;1 [04]
|
||||
bld shift, 7 ;1 [05]
|
||||
didUnstuff7: ;- [05]
|
||||
cpi shift, 0x04 ;1 [06] 0b00000100
|
||||
brlo unstuff7 ;1 [07]
|
||||
eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
|
||||
nop ;1 [09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample bit 0
|
||||
st y+, x3 ;2 [01+02] store data
|
||||
eor x2, x1 ;1 [03]
|
||||
bst x2, USBMINUS ;1 [04]
|
||||
bld shift, 0 ;1 [05]
|
||||
subi cnt, 1 ;1 [06]
|
||||
brcs ignorePacket ;1 [07]
|
||||
rjmp rxLoop ;2 [08]
|
||||
;-----------------------------------------------------
|
||||
unstuff4: ;- [08]
|
||||
andi x3, ~0x10 ;1 [09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
|
||||
andi x1, USBMASK ;1 [01]
|
||||
breq se0 ;1 [02] SE0 check for stuffed bit 4
|
||||
ori shift, 0x10 ;1 [03]
|
||||
rjmp didUnstuff4 ;2 [04]
|
||||
;-----------------------------------------------------
|
||||
unstuff5: ;- [08]
|
||||
ori shift, 0x20 ;1 [09]
|
||||
in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
|
||||
andi x2, USBMASK ;1 [01]
|
||||
breq se0 ;1 [02] SE0 check for stuffed bit 5
|
||||
andi x3, ~0x20 ;1 [03]
|
||||
rjmp didUnstuff5 ;2 [04]
|
||||
;-----------------------------------------------------
|
||||
unstuff6: ;- [08]
|
||||
andi x3, ~0x40 ;1 [09]
|
||||
in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
|
||||
andi x1, USBMASK ;1 [01]
|
||||
breq se0 ;1 [02] SE0 check for stuffed bit 6
|
||||
ori shift, 0x40 ;1 [03]
|
||||
rjmp didUnstuff6 ;2 [04]
|
||||
;-----------------------------------------------------
|
||||
unstuff7: ;- [08]
|
||||
andi x3, ~0x80 ;1 [09]
|
||||
in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
|
||||
andi x2, USBMASK ;1 [01]
|
||||
breq se0 ;1 [02] SE0 check for stuffed bit 7
|
||||
ori shift, 0x80 ;1 [03]
|
||||
rjmp didUnstuff7 ;2 [04]
|
||||
;----------------------------------------------------------------------------
|
||||
; Processing of received packet (numbers in brackets are cycles after center of SE0)
|
||||
;----------------------------------------------------------------------------
|
||||
;This is the only non-error exit point for the software receiver loop
|
||||
;we don't check any CRCs here because there is no time left.
|
||||
#define token x1
|
||||
se0: ;- [04]
|
||||
subi cnt, USB_BUFSIZE ;1 [05]
|
||||
neg cnt ;1 [06]
|
||||
cpi cnt, 3 ;1 [07]
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [08]
|
||||
USB_STORE_PENDING(x2) ;1 [09] clear pending intr and check flag later. SE0 should be over.
|
||||
brlo doReturn ;1 [10] this is probably an ACK, NAK or similar packet
|
||||
sub YL, cnt ;1 [11]
|
||||
sbci YH, 0 ;1 [12]
|
||||
ld token, y ;2 [13+14]
|
||||
cpi token, USBPID_DATA0 ;1 [15]
|
||||
breq handleData ;1 [16]
|
||||
cpi token, USBPID_DATA1 ;1 [17]
|
||||
breq handleData ;1 [18]
|
||||
ldd x2, y+1 ;2 [19+20] ADDR and 1 bit endpoint number
|
||||
mov x3, x2 ;1 [21] store for endpoint number
|
||||
andi x2, 0x7f ;1 [22] x2 is now ADDR
|
||||
lds shift, usbDeviceAddr ;2 [23+24]
|
||||
cp x2, shift ;1 [25]
|
||||
brne ignorePacket ;1 [26] packet for different address
|
||||
cpi token, USBPID_IN ;1 [27]
|
||||
breq handleIn ;1 [28]
|
||||
cpi token, USBPID_SETUP ;1 [29]
|
||||
breq handleSetupOrOut ;1 [30]
|
||||
cpi token, USBPID_OUT ;1 [31]
|
||||
breq handleSetupOrOut ;1 [32]
|
||||
; rjmp ignorePacket ; fallthrough, should not happen anyway.
|
||||
ignorePacket: ;- [32]
|
||||
clr shift ;1 [33]
|
||||
sts usbCurrentTok, shift ;2 [34+35]
|
||||
doReturn:
|
||||
pop x4
|
||||
pop cnt
|
||||
pop bitcnt
|
||||
pop x3
|
||||
pop x2
|
||||
pop x1
|
||||
pop shift
|
||||
pop YH
|
||||
sofError:
|
||||
pop YL
|
||||
out SREG, YL
|
||||
pop YL
|
||||
reti
|
||||
;-------------------------------------------------------------------------
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
handleIn3: ;- [42]
|
||||
lds cnt, usbTxLen3 ;2 [43+44]
|
||||
sbrc cnt, 4 ;1 [45]
|
||||
rjmp sendCntAndReti ;1 [46] 46 + 16 = 62 until SOP
|
||||
sts usbTxLen3, x1 ;2 [47+48] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf3) ;1 [49]
|
||||
ldi YH, hi8(usbTxBuf3) ;1 [50]
|
||||
rjmp usbSendAndReti ;1 [51] 51 + 13 = 64 until SOP
|
||||
#endif
|
||||
|
||||
;Setup and Out are followed by a data packet two bit times (20 cycles) after
|
||||
;the end of SE0. The sync code allows up to 50 cycles delay from the start of
|
||||
;the sync pattern until the first bit is sampled. That's a total of 70 cycles.
|
||||
handleSetupOrOut: ;[31/33]
|
||||
#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
|
||||
sbrc x3, 7 ;[32] skip if endpoint 0
|
||||
ldi token, -1 ;[33] indicate that this is endpoint 1 OUT
|
||||
#endif
|
||||
sts usbCurrentTok, token ;[34+35]
|
||||
pop x4 ;[36+37]
|
||||
pop cnt ;[38+39]
|
||||
pop bitcnt ;[40+41]
|
||||
pop x3 ;[42+43]
|
||||
pop x2 ;[44+45]
|
||||
pop x1 ;[46+47]
|
||||
pop shift ;[48+49]
|
||||
pop YH ;[50+51]
|
||||
USB_LOAD_PENDING(YL) ;[52]
|
||||
sbrc YL, USB_INTR_PENDING_BIT ;[53] check whether data is already arriving
|
||||
rjmp waitForJ ;[54] save the pops and pushes -- a new interrupt is aready pending
|
||||
rjmp sofError ;[55] not an error, but it does the pops and reti we want
|
||||
;--------------------------------------------------------------------
|
||||
handleData: ;- [16/18]
|
||||
lds token, usbCurrentTok ;2 [19+20]
|
||||
tst token ;1 [21]
|
||||
breq doReturn ;1 [22]
|
||||
lds x2, usbRxLen ;2 [23+24]
|
||||
tst x2 ;1 [25]
|
||||
brne sendNakAndReti ;1 [26]
|
||||
; 2006-03-11: The following two lines fix a problem where the device was not
|
||||
; recognized if usbPoll() was called less frequently than once every 4 ms.
|
||||
cpi cnt, 4 ;1 [27] 0 sized data packets are status phase only -- ignore and ack
|
||||
brmi sendAckAndReti ;1 [28] keep rx buffer clean -- we must not NAK next SETUP
|
||||
sts usbRxLen, cnt ;2 [29+30] store received data, swap buffers
|
||||
sts usbRxToken, token ;2 [31+23]
|
||||
lds x2, usbInputBufOffset ;2 [33+34] swap buffers
|
||||
ldi cnt, USB_BUFSIZE ;1 [35]
|
||||
sub cnt, x2 ;1 [36]
|
||||
sts usbInputBufOffset, cnt ;2 [37+38] buffers now swapped
|
||||
rjmp sendAckAndReti ;1 [39] 39 + 17 = 56 until SOP
|
||||
;--------------------------------------------------------------------
|
||||
;We don't send any data as long as the C code has not processed the current
|
||||
;input data and potentially updated the output data. That's more efficient
|
||||
;in terms of code size than clearing the tx buffers when a packet is received.
|
||||
handleIn: ;- [29]
|
||||
lds x1, usbRxLen ;2 [30+31]
|
||||
cpi x1, 1 ;1 [32] negative values are flow control, 0 means "buffer free"
|
||||
brge sendNakAndReti ;1 [33] unprocessed input packet?
|
||||
ldi x1, USBPID_NAK ;1 [34] prepare value for usbTxLen
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT
|
||||
sbrc x3, 7 ;1 [35] x3 contains addr + endpoint
|
||||
rjmp handleIn1 ;1 [36]
|
||||
#endif
|
||||
lds cnt, usbTxLen ;2 [37+38]
|
||||
sbrc cnt, 4 ;2 [39] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;1 [40] 42 + 16 = 58 until SOP
|
||||
sts usbTxLen, x1 ;2 [41+42] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf) ;1 [43]
|
||||
ldi YH, hi8(usbTxBuf) ;1 [44]
|
||||
rjmp usbSendAndReti ;1 [45] 45 + 13 = 58 until SOP
|
||||
;---------------------------------------------------------------------------------------
|
||||
; Comment about when to set usbTxLen to USBPID_NAK:
|
||||
; We should set it back when we receive the ACK from the host. This would
|
||||
; be simple to implement: One static variable which stores whether the last
|
||||
; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
|
||||
; ACK. However, we set it back immediately when we send the package,
|
||||
; assuming that no error occurs and the host sends an ACK. We save one byte
|
||||
; RAM this way and avoid potential problems with endless retries. The rest of
|
||||
; the driver assumes error-free transfers anyway.
|
||||
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
|
||||
handleIn1: ;- [37]
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
|
||||
ldd x2, y+2 ;2 [38+39]
|
||||
sbrc x2, 0 ;2 [40]
|
||||
rjmp handleIn3 ;1 [41]
|
||||
#endif
|
||||
lds cnt, usbTxLen1 ;2 [42+43]
|
||||
sbrc cnt, 4 ;2 [44] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;1 [45] 45 + 16 = 61 until SOP
|
||||
sts usbTxLen1, x1 ;2 [46+47] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf1) ;1 [48]
|
||||
ldi YH, hi8(usbTxBuf1) ;1 [49]
|
||||
rjmp usbSendAndReti ;1 [50] 50 + 13 + 63 until SOP
|
||||
#endif
|
||||
;---------------------------------------------------------------------------
|
||||
; USB spec says:
|
||||
; idle = J
|
||||
; J = (D+ = 0), (D- = 1)
|
||||
; K = (D+ = 1), (D- = 0)
|
||||
; Spec allows 7.5 bit times from EOP to SOP for replies
|
||||
;---------------------------------------------------------------------------
|
||||
bitstuffN: ;- [04]
|
||||
eor x1, x4 ;1 [05]
|
||||
clr x2 ;1 [06]
|
||||
nop ;1 [07]
|
||||
rjmp didStuffN ;1 [08]
|
||||
;---------------------------------------------------------------------------
|
||||
bitstuff6: ;- [04]
|
||||
eor x1, x4 ;1 [05]
|
||||
clr x2 ;1 [06]
|
||||
rjmp didStuff6 ;1 [07]
|
||||
;---------------------------------------------------------------------------
|
||||
bitstuff7: ;- [02]
|
||||
eor x1, x4 ;1 [03]
|
||||
clr x2 ;1 [06]
|
||||
nop ;1 [05]
|
||||
rjmp didStuff7 ;1 [06]
|
||||
;---------------------------------------------------------------------------
|
||||
sendNakAndReti: ;- [-19]
|
||||
ldi x3, USBPID_NAK ;1 [-18]
|
||||
rjmp sendX3AndReti ;1 [-17]
|
||||
;---------------------------------------------------------------------------
|
||||
sendAckAndReti: ;- [-17]
|
||||
ldi cnt, USBPID_ACK ;1 [-16]
|
||||
sendCntAndReti: ;- [-16]
|
||||
mov x3, cnt ;1 [-15]
|
||||
sendX3AndReti: ;- [-15]
|
||||
ldi YL, 20 ;1 [-14] x3==r20 address is 20
|
||||
ldi YH, 0 ;1 [-13]
|
||||
ldi cnt, 2 ;1 [-12]
|
||||
; rjmp usbSendAndReti fallthrough
|
||||
;---------------------------------------------------------------------------
|
||||
;usbSend:
|
||||
;pointer to data in 'Y'
|
||||
;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
|
||||
;uses: x1...x4, btcnt, shift, cnt, Y
|
||||
;Numbers in brackets are time since first bit of sync pattern is sent
|
||||
;We need not to match the transfer rate exactly because the spec demands
|
||||
;only 1.5% precision anyway.
|
||||
usbSendAndReti: ;- [-13] 13 cycles until SOP
|
||||
in x2, USBDDR ;1 [-12]
|
||||
ori x2, USBMASK ;1 [-11]
|
||||
sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
|
||||
in x1, USBOUT ;1 [-08] port mirror for tx loop
|
||||
out USBDDR, x2 ;1 [-07] <- acquire bus
|
||||
; need not init x2 (bitstuff history) because sync starts with 0
|
||||
ldi x4, USBMASK ;1 [-06] exor mask
|
||||
ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
|
||||
ldi bitcnt, 6 ;1 [-04]
|
||||
txBitLoop: ;- [-04] [06]
|
||||
sbrs shift, 0 ;1 [-03] [07]
|
||||
eor x1, x4 ;1 [-02] [08]
|
||||
ror shift ;1 [-01] [09]
|
||||
didStuffN: ;- [09]
|
||||
out USBOUT, x1 ;1 [00] [10] <-- out N
|
||||
ror x2 ;1 [01]
|
||||
cpi x2, 0xfc ;1 [02]
|
||||
brcc bitstuffN ;1 [03]
|
||||
dec bitcnt ;1 [04]
|
||||
brne txBitLoop ;1 [05]
|
||||
sbrs shift, 0 ;1 [06]
|
||||
eor x1, x4 ;1 [07]
|
||||
ror shift ;1 [08]
|
||||
didStuff6: ;- [08]
|
||||
nop ;1 [09]
|
||||
out USBOUT, x1 ;1 [00] [10] <-- out 6
|
||||
ror x2 ;1 [01]
|
||||
cpi x2, 0xfc ;1 [02]
|
||||
brcc bitstuff6 ;1 [03]
|
||||
sbrs shift, 0 ;1 [04]
|
||||
eor x1, x4 ;1 [05]
|
||||
ror shift ;1 [06]
|
||||
ror x2 ;1 [07]
|
||||
didStuff7: ;- [07]
|
||||
ldi bitcnt, 6 ;1 [08]
|
||||
cpi x2, 0xfc ;1 [09]
|
||||
out USBOUT, x1 ;1 [00] [10] <-- out 7
|
||||
brcc bitstuff7 ;1 [01]
|
||||
ld shift, y+ ;2 [02+03]
|
||||
dec cnt ;1 [04]
|
||||
brne txBitLoop ;1 [05]
|
||||
makeSE0:
|
||||
cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
|
||||
lds x2, usbNewDeviceAddr;2 [07+08]
|
||||
;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
||||
;set address only after data packet was sent, not after handshake
|
||||
subi YL, 2 ;1 [09]
|
||||
out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
|
||||
sbci YH, 0 ;1 [01]
|
||||
breq skipAddrAssign ;1 [02]
|
||||
sts usbDeviceAddr, x2 ;2 [03+04] if not skipped: SE0 is one cycle longer
|
||||
;----------------------------------------------------------------------------
|
||||
;end of usbDeviceAddress transfer
|
||||
skipAddrAssign: ;- [03/04]
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [04] int0 occurred during TX -- clear pending flag
|
||||
USB_STORE_PENDING(x2) ;1 [05]
|
||||
ori x1, USBIDLE ;1 [06]
|
||||
in x2, USBDDR ;1 [07]
|
||||
cbr x2, USBMASK ;1 [08] set both pins to input
|
||||
mov x3, x1 ;1 [09]
|
||||
cbr x3, USBMASK ;1 [10] configure no pullup on both pins
|
||||
ldi x4, 3 ;1 [11]
|
||||
se0Delay: ;- [11] [14]
|
||||
dec x4 ;1 [12] [15]
|
||||
brne se0Delay ;1 [13] [16]
|
||||
nop2 ;2 [17+18]
|
||||
out USBOUT, x1 ;1 [19] <--out J (idle) -- end of SE0 (EOP sig.)
|
||||
out USBDDR, x2 ;1 [20] <--release bus now
|
||||
out USBOUT, x3 ;1 [21] <--ensure no pull-up resistors are active
|
||||
rjmp doReturn ;1 [22]
|
||||
;---------------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,472 @@
|
|||
/* Name: usbdrvasm16.S
|
||||
* Project: AVR USB driver
|
||||
* Author: Christian Starkjohann
|
||||
* Creation Date: 2007-06-15
|
||||
* Tabsize: 4
|
||||
* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
|
||||
* License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
|
||||
* Revision: $Id: usbdrvasm16.S,v 1.1 2013-04-25 02:18:15 cvs Exp $
|
||||
*/
|
||||
|
||||
/* Do not link this file! Link usbdrvasm.S instead, which includes the
|
||||
* appropriate implementation!
|
||||
*/
|
||||
|
||||
/*
|
||||
General Description:
|
||||
This file is the 16 MHz version of the asssembler part of the USB driver. It
|
||||
requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
|
||||
oscillator).
|
||||
|
||||
See usbdrv.h for a description of the entire driver.
|
||||
|
||||
Since almost all of this code is timing critical, don't change unless you
|
||||
really know what you are doing! Many parts require not only a maximum number
|
||||
of CPU cycles, but even an exact number of cycles!
|
||||
*/
|
||||
|
||||
;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
|
||||
;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
|
||||
; Numbers in brackets are clocks counted from center of last sync bit
|
||||
; when instruction starts
|
||||
|
||||
USB_INTR_VECTOR:
|
||||
;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
|
||||
push YL ;[-25] push only what is necessary to sync with edge ASAP
|
||||
in YL, SREG ;[-23]
|
||||
push YL ;[-22]
|
||||
push YH ;[-20]
|
||||
;----------------------------------------------------------------------------
|
||||
; Synchronize with sync pattern:
|
||||
;----------------------------------------------------------------------------
|
||||
;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
|
||||
;sync up with J to K edge during sync pattern -- use fastest possible loops
|
||||
;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
|
||||
waitForJ:
|
||||
sbis USBIN, USBMINUS ;[-18] wait for D- == 1
|
||||
rjmp waitForJ
|
||||
waitForK:
|
||||
;The following code results in a sampling window of < 1/4 bit which meets the spec.
|
||||
sbis USBIN, USBMINUS ;[-15]
|
||||
rjmp foundK ;[-14]
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
#if USB_COUNT_SOF
|
||||
lds YL, usbSofCount
|
||||
inc YL
|
||||
sts usbSofCount, YL
|
||||
#endif /* USB_COUNT_SOF */
|
||||
rjmp sofError
|
||||
foundK: ;[-12]
|
||||
;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
|
||||
;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
|
||||
;are cycles from center of first sync (double K) bit after the instruction
|
||||
push bitcnt ;[-12]
|
||||
; [---] ;[-11]
|
||||
lds YL, usbInputBufOffset;[-10]
|
||||
; [---] ;[-9]
|
||||
clr YH ;[-8]
|
||||
subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
|
||||
sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
|
||||
push shift ;[-5]
|
||||
; [---] ;[-4]
|
||||
ldi bitcnt, 0x55 ;[-3] [rx loop init]
|
||||
sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
|
||||
rjmp haveTwoBitsK ;[-1]
|
||||
pop shift ;[0] undo the push from before
|
||||
pop bitcnt ;[2] undo the push from before
|
||||
rjmp waitForK ;[4] this was not the end of sync, retry
|
||||
; The entire loop from waitForK until rjmp waitForK above must not exceed two
|
||||
; bit times (= 21 cycles).
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; push more registers and initialize values while we sample the first bits:
|
||||
;----------------------------------------------------------------------------
|
||||
haveTwoBitsK:
|
||||
push x1 ;[1]
|
||||
push x2 ;[3]
|
||||
push x3 ;[5]
|
||||
ldi shift, 0 ;[7]
|
||||
ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
|
||||
push x4 ;[9] == leap
|
||||
|
||||
in x1, USBIN ;[11] <-- sample bit 0
|
||||
andi x1, USBMASK ;[12]
|
||||
bst x1, USBMINUS ;[13]
|
||||
bld shift, 7 ;[14]
|
||||
push cnt ;[15]
|
||||
ldi leap, 0 ;[17] [rx loop init]
|
||||
ldi cnt, USB_BUFSIZE;[18] [rx loop init]
|
||||
rjmp rxbit1 ;[19] arrives at [21]
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; Receiver loop (numbers in brackets are cycles within byte after instr)
|
||||
;----------------------------------------------------------------------------
|
||||
|
||||
unstuff6:
|
||||
andi x2, USBMASK ;[03]
|
||||
ori x3, 1<<6 ;[04] will not be shifted any more
|
||||
andi shift, ~0x80;[05]
|
||||
mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
|
||||
subi leap, 3 ;[07] since this is a short (10 cycle) bit, enforce leap bit
|
||||
rjmp didUnstuff6 ;[08]
|
||||
|
||||
unstuff7:
|
||||
ori x3, 1<<7 ;[09] will not be shifted any more
|
||||
in x2, USBIN ;[00] [10] re-sample bit 7
|
||||
andi x2, USBMASK ;[01]
|
||||
andi shift, ~0x80;[02]
|
||||
subi leap, 3 ;[03] since this is a short (10 cycle) bit, enforce leap bit
|
||||
rjmp didUnstuff7 ;[04]
|
||||
|
||||
unstuffEven:
|
||||
ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
|
||||
in x1, USBIN ;[00] [10]
|
||||
andi shift, ~0x80;[01]
|
||||
andi x1, USBMASK ;[02]
|
||||
breq se0 ;[03]
|
||||
subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
|
||||
nop ;[05]
|
||||
rjmp didUnstuffE ;[06]
|
||||
|
||||
unstuffOdd:
|
||||
ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
|
||||
in x2, USBIN ;[00] [10]
|
||||
andi shift, ~0x80;[01]
|
||||
andi x2, USBMASK ;[02]
|
||||
breq se0 ;[03]
|
||||
subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
|
||||
nop ;[05]
|
||||
rjmp didUnstuffO ;[06]
|
||||
|
||||
rxByteLoop:
|
||||
andi x1, USBMASK ;[03]
|
||||
eor x2, x1 ;[04]
|
||||
subi leap, 1 ;[05]
|
||||
brpl skipLeap ;[06]
|
||||
subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
|
||||
nop ;1
|
||||
skipLeap:
|
||||
subi x2, 1 ;[08]
|
||||
ror shift ;[09]
|
||||
didUnstuff6:
|
||||
cpi shift, 0xfc ;[10]
|
||||
in x2, USBIN ;[00] [11] <-- sample bit 7
|
||||
brcc unstuff6 ;[01]
|
||||
andi x2, USBMASK ;[02]
|
||||
eor x1, x2 ;[03]
|
||||
subi x1, 1 ;[04]
|
||||
ror shift ;[05]
|
||||
didUnstuff7:
|
||||
cpi shift, 0xfc ;[06]
|
||||
brcc unstuff7 ;[07]
|
||||
eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
|
||||
st y+, x3 ;[09] store data
|
||||
rxBitLoop:
|
||||
in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
|
||||
andi x1, USBMASK ;[01]
|
||||
eor x2, x1 ;[02]
|
||||
andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
|
||||
subi x2, 1 ;[04]
|
||||
ror shift ;[05]
|
||||
cpi shift, 0xfc ;[06]
|
||||
brcc unstuffEven ;[07]
|
||||
didUnstuffE:
|
||||
lsr x3 ;[08]
|
||||
lsr x3 ;[09]
|
||||
rxbit1:
|
||||
in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
|
||||
andi x2, USBMASK ;[01]
|
||||
breq se0 ;[02]
|
||||
eor x1, x2 ;[03]
|
||||
subi x1, 1 ;[04]
|
||||
ror shift ;[05]
|
||||
cpi shift, 0xfc ;[06]
|
||||
brcc unstuffOdd ;[07]
|
||||
didUnstuffO:
|
||||
subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
|
||||
brcs rxBitLoop ;[09]
|
||||
|
||||
subi cnt, 1 ;[10]
|
||||
in x1, USBIN ;[00] [11] <-- sample bit 6
|
||||
brcc rxByteLoop ;[01]
|
||||
rjmp ignorePacket; overflow
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; Processing of received packet (numbers in brackets are cycles after center of SE0)
|
||||
;----------------------------------------------------------------------------
|
||||
;This is the only non-error exit point for the software receiver loop
|
||||
;we don't check any CRCs here because there is no time left.
|
||||
#define token x1
|
||||
se0:
|
||||
subi cnt, USB_BUFSIZE ;[5]
|
||||
neg cnt ;[6]
|
||||
cpi cnt, 3 ;[7]
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
|
||||
USB_STORE_PENDING(x2) ;[9] clear pending intr and check flag later. SE0 should be over.
|
||||
brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
|
||||
sub YL, cnt ;[11]
|
||||
sbci YH, 0 ;[12]
|
||||
ld token, y ;[13]
|
||||
cpi token, USBPID_DATA0 ;[15]
|
||||
breq handleData ;[16]
|
||||
cpi token, USBPID_DATA1 ;[17]
|
||||
breq handleData ;[18]
|
||||
ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
|
||||
mov x3, x2 ;[21] store for endpoint number
|
||||
andi x2, 0x7f ;[22] x2 is now ADDR
|
||||
lds shift, usbDeviceAddr;[23]
|
||||
cp x2, shift ;[25]
|
||||
overflow: ; This is a hack: brcs overflow will never have Z flag set
|
||||
brne ignorePacket ;[26] packet for different address
|
||||
cpi token, USBPID_IN ;[27]
|
||||
breq handleIn ;[28]
|
||||
cpi token, USBPID_SETUP ;[29]
|
||||
breq handleSetupOrOut ;[30]
|
||||
cpi token, USBPID_OUT ;[31]
|
||||
breq handleSetupOrOut ;[32]
|
||||
; rjmp ignorePacket ;fallthrough, should not happen anyway.
|
||||
|
||||
ignorePacket:
|
||||
clr shift
|
||||
sts usbCurrentTok, shift
|
||||
doReturn:
|
||||
pop cnt
|
||||
pop x4
|
||||
pop x3
|
||||
pop x2
|
||||
pop x1
|
||||
pop shift
|
||||
pop bitcnt
|
||||
sofError:
|
||||
pop YH
|
||||
pop YL
|
||||
out SREG, YL
|
||||
pop YL
|
||||
reti
|
||||
|
||||
;Setup and Out are followed by a data packet two bit times (16 cycles) after
|
||||
;the end of SE0. The sync code allows up to 40 cycles delay from the start of
|
||||
;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
|
||||
handleSetupOrOut: ;[34]
|
||||
#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
|
||||
sbrc x3, 7 ;[34] skip if endpoint 0
|
||||
ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
|
||||
#endif
|
||||
sts usbCurrentTok, token;[36]
|
||||
pop cnt ;[38]
|
||||
pop x4 ;[40]
|
||||
pop x3 ;[42]
|
||||
pop x2 ;[44]
|
||||
pop x1 ;[46]
|
||||
pop shift ;[48]
|
||||
pop bitcnt ;[50]
|
||||
USB_LOAD_PENDING(YL) ;[52]
|
||||
sbrc YL, USB_INTR_PENDING_BIT;[53] check whether data is already arriving
|
||||
rjmp waitForJ ;[54] save the pops and pushes -- a new interrupt is aready pending
|
||||
rjmp sofError ;[55] not an error, but it does the pops and reti we want
|
||||
|
||||
|
||||
handleData:
|
||||
lds token, usbCurrentTok;[20]
|
||||
tst token ;[22]
|
||||
breq doReturn ;[23]
|
||||
lds x2, usbRxLen ;[24]
|
||||
tst x2 ;[26]
|
||||
brne sendNakAndReti ;[27]
|
||||
; 2006-03-11: The following two lines fix a problem where the device was not
|
||||
; recognized if usbPoll() was called less frequently than once every 4 ms.
|
||||
cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
|
||||
brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
|
||||
sts usbRxLen, cnt ;[30] store received data, swap buffers
|
||||
sts usbRxToken, token ;[32]
|
||||
lds x2, usbInputBufOffset;[34] swap buffers
|
||||
ldi cnt, USB_BUFSIZE ;[36]
|
||||
sub cnt, x2 ;[37]
|
||||
sts usbInputBufOffset, cnt;[38] buffers now swapped
|
||||
rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
|
||||
|
||||
handleIn:
|
||||
;We don't send any data as long as the C code has not processed the current
|
||||
;input data and potentially updated the output data. That's more efficient
|
||||
;in terms of code size than clearing the tx buffers when a packet is received.
|
||||
lds x1, usbRxLen ;[30]
|
||||
cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
|
||||
brge sendNakAndReti ;[33] unprocessed input packet?
|
||||
ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT
|
||||
sbrc x3, 7 ;[35] x3 contains addr + endpoint
|
||||
rjmp handleIn1 ;[36]
|
||||
#endif
|
||||
lds cnt, usbTxLen ;[37]
|
||||
sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
|
||||
sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf) ;[43]
|
||||
ldi YH, hi8(usbTxBuf) ;[44]
|
||||
rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
|
||||
|
||||
; Comment about when to set usbTxLen to USBPID_NAK:
|
||||
; We should set it back when we receive the ACK from the host. This would
|
||||
; be simple to implement: One static variable which stores whether the last
|
||||
; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
|
||||
; ACK. However, we set it back immediately when we send the package,
|
||||
; assuming that no error occurs and the host sends an ACK. We save one byte
|
||||
; RAM this way and avoid potential problems with endless retries. The rest of
|
||||
; the driver assumes error-free transfers anyway.
|
||||
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
|
||||
handleIn1: ;[38]
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
|
||||
ldd x2, y+2 ;[38]
|
||||
sbrc x2, 0 ;[40]
|
||||
rjmp handleIn3 ;[41]
|
||||
#endif
|
||||
lds cnt, usbTxLen1 ;[42]
|
||||
sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
|
||||
sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf1) ;[48]
|
||||
ldi YH, hi8(usbTxBuf1) ;[49]
|
||||
rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
|
||||
#endif
|
||||
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
handleIn3:
|
||||
lds cnt, usbTxLen3 ;[43]
|
||||
sbrc cnt, 4 ;[45]
|
||||
rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
|
||||
sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf3) ;[49]
|
||||
ldi YH, hi8(usbTxBuf3) ;[50]
|
||||
rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
|
||||
#endif
|
||||
|
||||
; USB spec says:
|
||||
; idle = J
|
||||
; J = (D+ = 0), (D- = 1)
|
||||
; K = (D+ = 1), (D- = 0)
|
||||
; Spec allows 7.5 bit times from EOP to SOP for replies
|
||||
|
||||
bitstuffN:
|
||||
eor x1, x4 ;[5]
|
||||
ldi x2, 0 ;[6]
|
||||
nop2 ;[7]
|
||||
nop ;[9]
|
||||
out USBOUT, x1 ;[10] <-- out
|
||||
rjmp didStuffN ;[0]
|
||||
|
||||
bitstuff6:
|
||||
eor x1, x4 ;[4]
|
||||
ldi x2, 0 ;[5]
|
||||
nop2 ;[6] C is zero (brcc)
|
||||
rjmp didStuff6 ;[8]
|
||||
|
||||
bitstuff7:
|
||||
eor x1, x4 ;[3]
|
||||
ldi x2, 0 ;[4]
|
||||
rjmp didStuff7 ;[5]
|
||||
|
||||
|
||||
sendNakAndReti:
|
||||
ldi x3, USBPID_NAK ;[-18]
|
||||
rjmp sendX3AndReti ;[-17]
|
||||
sendAckAndReti:
|
||||
ldi cnt, USBPID_ACK ;[-17]
|
||||
sendCntAndReti:
|
||||
mov x3, cnt ;[-16]
|
||||
sendX3AndReti:
|
||||
ldi YL, 20 ;[-15] x3==r20 address is 20
|
||||
ldi YH, 0 ;[-14]
|
||||
ldi cnt, 2 ;[-13]
|
||||
; rjmp usbSendAndReti fallthrough
|
||||
|
||||
;usbSend:
|
||||
;pointer to data in 'Y'
|
||||
;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
|
||||
;uses: x1...x4, btcnt, shift, cnt, Y
|
||||
;Numbers in brackets are time since first bit of sync pattern is sent
|
||||
;We don't match the transfer rate exactly (don't insert leap cycles every third
|
||||
;byte) because the spec demands only 1.5% precision anyway.
|
||||
usbSendAndReti: ; 12 cycles until SOP
|
||||
in x2, USBDDR ;[-12]
|
||||
ori x2, USBMASK ;[-11]
|
||||
sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
|
||||
in x1, USBOUT ;[-8] port mirror for tx loop
|
||||
out USBDDR, x2 ;[-7] <- acquire bus
|
||||
; need not init x2 (bitstuff history) because sync starts with 0
|
||||
ldi x4, USBMASK ;[-6] exor mask
|
||||
ldi shift, 0x80 ;[-5] sync byte is first byte sent
|
||||
txByteLoop:
|
||||
ldi bitcnt, 0x2a ;[-4] [6] binary 00101010
|
||||
txBitLoop:
|
||||
sbrs shift, 0 ;[-3] [7]
|
||||
eor x1, x4 ;[-2] [8]
|
||||
out USBOUT, x1 ;[-1] [9] <-- out N
|
||||
ror shift ;[0] [10]
|
||||
ror x2 ;[1]
|
||||
didStuffN:
|
||||
cpi x2, 0xfc ;[2]
|
||||
brcc bitstuffN ;[3]
|
||||
lsr bitcnt ;[4]
|
||||
brcc txBitLoop ;[5]
|
||||
brne txBitLoop ;[6]
|
||||
|
||||
sbrs shift, 0 ;[7]
|
||||
eor x1, x4 ;[8]
|
||||
ror shift ;[9]
|
||||
didStuff6:
|
||||
out USBOUT, x1 ;[-1] [10] <-- out 6
|
||||
ror x2 ;[0] [11]
|
||||
cpi x2, 0xfc ;[1]
|
||||
brcc bitstuff6 ;[2]
|
||||
sbrs shift, 0 ;[3]
|
||||
eor x1, x4 ;[4]
|
||||
ror shift ;[5]
|
||||
ror x2 ;[6]
|
||||
didStuff7:
|
||||
nop ;[7]
|
||||
nop2 ;[8]
|
||||
out USBOUT, x1 ;[-1][10] <-- out 7
|
||||
cpi x2, 0xfc ;[0] [11]
|
||||
brcc bitstuff7 ;[1]
|
||||
ld shift, y+ ;[2]
|
||||
dec cnt ;[4]
|
||||
brne txByteLoop ;[4]
|
||||
;make SE0:
|
||||
cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
|
||||
lds x2, usbNewDeviceAddr;[8]
|
||||
out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
|
||||
;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
||||
;set address only after data packet was sent, not after handshake
|
||||
subi YL, 2 ;[0]
|
||||
sbci YH, 0 ;[1]
|
||||
breq skipAddrAssign ;[2]
|
||||
sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
|
||||
skipAddrAssign:
|
||||
;end of usbDeviceAddress transfer
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
|
||||
USB_STORE_PENDING(x2) ;[5]
|
||||
ori x1, USBIDLE ;[6]
|
||||
in x2, USBDDR ;[7]
|
||||
cbr x2, USBMASK ;[8] set both pins to input
|
||||
mov x3, x1 ;[9]
|
||||
cbr x3, USBMASK ;[10] configure no pullup on both pins
|
||||
ldi x4, 4 ;[11]
|
||||
se0Delay:
|
||||
dec x4 ;[12] [15] [18] [21]
|
||||
brne se0Delay ;[13] [16] [19] [22]
|
||||
out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
|
||||
out USBDDR, x2 ;[24] <-- release bus now
|
||||
out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
|
||||
rjmp doReturn
|
||||
|
||||
|
|
@ -0,0 +1,580 @@
|
|||
/* Name: usbdrvasm165.S
|
||||
* Project: AVR USB driver
|
||||
* Author: Christian Starkjohann
|
||||
* Creation Date: 2007-04-22
|
||||
* Tabsize: 4
|
||||
* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
|
||||
* License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
|
||||
* Revision: $Id: usbdrvasm165.S,v 1.1 2013-04-25 02:18:15 cvs Exp $
|
||||
*/
|
||||
|
||||
/* Do not link this file! Link usbdrvasm.S instead, which includes the
|
||||
* appropriate implementation!
|
||||
*/
|
||||
|
||||
/*
|
||||
General Description:
|
||||
This file is the 16.5 MHz version of the USB driver. It is intended for the
|
||||
ATTiny45 and similar controllers running on 16.5 MHz internal RC oscillator.
|
||||
This version contains a phase locked loop in the receiver routine to cope with
|
||||
slight clock rate deviations of up to +/- 1%.
|
||||
|
||||
See usbdrv.h for a description of the entire driver.
|
||||
|
||||
Since almost all of this code is timing critical, don't change unless you
|
||||
really know what you are doing! Many parts require not only a maximum number
|
||||
of CPU cycles, but even an exact number of cycles!
|
||||
*/
|
||||
|
||||
;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
|
||||
;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
|
||||
;max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable
|
||||
;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes
|
||||
;nominal frequency: 16.5 MHz -> 11 cycles per bit
|
||||
; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%)
|
||||
; Numbers in brackets are clocks counted from center of last sync bit
|
||||
; when instruction starts
|
||||
|
||||
|
||||
USB_INTR_VECTOR:
|
||||
;order of registers pushed: r0, SREG [sofError], YL, YH, shift, x1, x2, x3, x4, cnt
|
||||
push r0 ;[-23] push only what is necessary to sync with edge ASAP
|
||||
in r0, SREG ;[-21]
|
||||
push r0 ;[-20]
|
||||
;----------------------------------------------------------------------------
|
||||
; Synchronize with sync pattern:
|
||||
;----------------------------------------------------------------------------
|
||||
;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
|
||||
;sync up with J to K edge during sync pattern -- use fastest possible loops
|
||||
;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
|
||||
waitForJ:
|
||||
sbis USBIN, USBMINUS ;[-18] wait for D- == 1
|
||||
rjmp waitForJ
|
||||
waitForK:
|
||||
;The following code results in a sampling window of < 1/4 bit which meets the spec.
|
||||
sbis USBIN, USBMINUS ;[-15]
|
||||
rjmp foundK ;[-14]
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
sbis USBIN, USBMINUS
|
||||
rjmp foundK
|
||||
#if USB_COUNT_SOF
|
||||
lds YL, usbSofCount
|
||||
inc YL
|
||||
sts usbSofCount, YL
|
||||
#endif /* USB_COUNT_SOF */
|
||||
rjmp sofError
|
||||
foundK: ;[-12]
|
||||
;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
|
||||
;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
|
||||
;are cycles from center of first sync (double K) bit after the instruction
|
||||
push YL ;[-12]
|
||||
; [---] ;[-11]
|
||||
push YH ;[-10]
|
||||
; [---] ;[-9]
|
||||
lds YL, usbInputBufOffset;[-8]
|
||||
; [---] ;[-7]
|
||||
clr YH ;[-6]
|
||||
subi YL, lo8(-(usbRxBuf));[-5] [rx loop init]
|
||||
sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init]
|
||||
mov r0, x2 ;[-3] [rx loop init]
|
||||
sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
|
||||
rjmp haveTwoBitsK ;[-1]
|
||||
pop YH ;[0] undo the pushes from before
|
||||
pop YL ;[2]
|
||||
rjmp waitForK ;[4] this was not the end of sync, retry
|
||||
; The entire loop from waitForK until rjmp waitForK above must not exceed two
|
||||
; bit times (= 22 cycles).
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; push more registers and initialize values while we sample the first bits:
|
||||
;----------------------------------------------------------------------------
|
||||
haveTwoBitsK: ;[1]
|
||||
push shift ;[1]
|
||||
push x1 ;[3]
|
||||
push x2 ;[5]
|
||||
push x3 ;[7]
|
||||
ldi shift, 0xff ;[9] [rx loop init]
|
||||
ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag
|
||||
|
||||
in x1, USBIN ;[11] <-- sample bit 0
|
||||
bst x1, USBMINUS ;[12]
|
||||
bld shift, 0 ;[13]
|
||||
push x4 ;[14] == phase
|
||||
; [---] ;[15]
|
||||
push cnt ;[16]
|
||||
; [---] ;[17]
|
||||
ldi phase, 0 ;[18] [rx loop init]
|
||||
ldi cnt, USB_BUFSIZE;[19] [rx loop init]
|
||||
rjmp rxbit1 ;[20]
|
||||
; [---] ;[21]
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; Receiver loop (numbers in brackets are cycles within byte after instr)
|
||||
;----------------------------------------------------------------------------
|
||||
/*
|
||||
byte oriented operations done during loop:
|
||||
bit 0: store data
|
||||
bit 1: SE0 check
|
||||
bit 2: overflow check
|
||||
bit 3: catch up
|
||||
bit 4: rjmp to achieve conditional jump range
|
||||
bit 5: PLL
|
||||
bit 6: catch up
|
||||
bit 7: jump, fixup bitstuff
|
||||
; 87 [+ 2] cycles
|
||||
------------------------------------------------------------------
|
||||
*/
|
||||
continueWithBit5:
|
||||
in x2, USBIN ;[055] <-- bit 5
|
||||
eor r0, x2 ;[056]
|
||||
or phase, r0 ;[057]
|
||||
sbrc phase, USBMINUS ;[058]
|
||||
lpm ;[059] optional nop3; modifies r0
|
||||
in phase, USBIN ;[060] <-- phase
|
||||
eor x1, x2 ;[061]
|
||||
bst x1, USBMINUS ;[062]
|
||||
bld shift, 5 ;[063]
|
||||
andi shift, 0x3f ;[064]
|
||||
in x1, USBIN ;[065] <-- bit 6
|
||||
breq unstuff5 ;[066] *** unstuff escape
|
||||
eor phase, x1 ;[067]
|
||||
eor x2, x1 ;[068]
|
||||
bst x2, USBMINUS ;[069]
|
||||
bld shift, 6 ;[070]
|
||||
didUnstuff6: ;[ ]
|
||||
in r0, USBIN ;[071] <-- phase
|
||||
cpi shift, 0x02 ;[072]
|
||||
brlo unstuff6 ;[073] *** unstuff escape
|
||||
didUnstuff5: ;[ ]
|
||||
nop2 ;[074]
|
||||
; [---] ;[075]
|
||||
in x2, USBIN ;[076] <-- bit 7
|
||||
eor x1, x2 ;[077]
|
||||
bst x1, USBMINUS ;[078]
|
||||
bld shift, 7 ;[079]
|
||||
didUnstuff7: ;[ ]
|
||||
eor r0, x2 ;[080]
|
||||
or phase, r0 ;[081]
|
||||
in r0, USBIN ;[082] <-- phase
|
||||
cpi shift, 0x04 ;[083]
|
||||
brsh rxLoop ;[084]
|
||||
; [---] ;[085]
|
||||
unstuff7: ;[ ]
|
||||
andi x3, ~0x80 ;[085]
|
||||
ori shift, 0x80 ;[086]
|
||||
in x2, USBIN ;[087] <-- sample stuffed bit 7
|
||||
nop ;[088]
|
||||
rjmp didUnstuff7 ;[089]
|
||||
; [---] ;[090]
|
||||
;[080]
|
||||
|
||||
unstuff5: ;[067]
|
||||
eor phase, x1 ;[068]
|
||||
andi x3, ~0x20 ;[069]
|
||||
ori shift, 0x20 ;[070]
|
||||
in r0, USBIN ;[071] <-- phase
|
||||
mov x2, x1 ;[072]
|
||||
nop ;[073]
|
||||
nop2 ;[074]
|
||||
; [---] ;[075]
|
||||
in x1, USBIN ;[076] <-- bit 6
|
||||
eor r0, x1 ;[077]
|
||||
or phase, r0 ;[078]
|
||||
eor x2, x1 ;[079]
|
||||
bst x2, USBMINUS ;[080]
|
||||
bld shift, 6 ;[081] no need to check bitstuffing, we just had one
|
||||
in r0, USBIN ;[082] <-- phase
|
||||
rjmp didUnstuff5 ;[083]
|
||||
; [---] ;[084]
|
||||
;[074]
|
||||
|
||||
unstuff6: ;[074]
|
||||
andi x3, ~0x40 ;[075]
|
||||
in x1, USBIN ;[076] <-- bit 6 again
|
||||
ori shift, 0x40 ;[077]
|
||||
nop2 ;[078]
|
||||
; [---] ;[079]
|
||||
rjmp didUnstuff6 ;[080]
|
||||
; [---] ;[081]
|
||||
;[071]
|
||||
|
||||
unstuff0: ;[013]
|
||||
eor r0, x2 ;[014]
|
||||
or phase, r0 ;[015]
|
||||
andi x2, USBMASK ;[016] check for SE0
|
||||
in r0, USBIN ;[017] <-- phase
|
||||
breq didUnstuff0 ;[018] direct jump to se0 would be too long
|
||||
andi x3, ~0x01 ;[019]
|
||||
ori shift, 0x01 ;[020]
|
||||
mov x1, x2 ;[021] mov existing sample
|
||||
in x2, USBIN ;[022] <-- bit 1 again
|
||||
rjmp didUnstuff0 ;[023]
|
||||
; [---] ;[024]
|
||||
;[014]
|
||||
|
||||
unstuff1: ;[024]
|
||||
eor r0, x1 ;[025]
|
||||
or phase, r0 ;[026]
|
||||
andi x3, ~0x02 ;[027]
|
||||
in r0, USBIN ;[028] <-- phase
|
||||
ori shift, 0x02 ;[029]
|
||||
mov x2, x1 ;[030]
|
||||
rjmp didUnstuff1 ;[031]
|
||||
; [---] ;[032]
|
||||
;[022]
|
||||
|
||||
unstuff2: ;[035]
|
||||
eor r0, x2 ;[036]
|
||||
or phase, r0 ;[037]
|
||||
andi x3, ~0x04 ;[038]
|
||||
in r0, USBIN ;[039] <-- phase
|
||||
ori shift, 0x04 ;[040]
|
||||
mov x1, x2 ;[041]
|
||||
rjmp didUnstuff2 ;[042]
|
||||
; [---] ;[043]
|
||||
;[033]
|
||||
|
||||
unstuff3: ;[043]
|
||||
in x2, USBIN ;[044] <-- bit 3 again
|
||||
eor r0, x2 ;[045]
|
||||
or phase, r0 ;[046]
|
||||
andi x3, ~0x08 ;[047]
|
||||
ori shift, 0x08 ;[048]
|
||||
nop ;[049]
|
||||
in r0, USBIN ;[050] <-- phase
|
||||
rjmp didUnstuff3 ;[051]
|
||||
; [---] ;[052]
|
||||
;[042]
|
||||
|
||||
unstuff4: ;[053]
|
||||
andi x3, ~0x10 ;[054]
|
||||
in x1, USBIN ;[055] <-- bit 4 again
|
||||
ori shift, 0x10 ;[056]
|
||||
rjmp didUnstuff4 ;[057]
|
||||
; [---] ;[058]
|
||||
;[048]
|
||||
|
||||
rxLoop: ;[085]
|
||||
eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others
|
||||
in x1, USBIN ;[000] <-- bit 0
|
||||
st y+, x3 ;[001]
|
||||
; [---] ;[002]
|
||||
eor r0, x1 ;[003]
|
||||
or phase, r0 ;[004]
|
||||
eor x2, x1 ;[005]
|
||||
in r0, USBIN ;[006] <-- phase
|
||||
ser x3 ;[007]
|
||||
bst x2, USBMINUS ;[008]
|
||||
bld shift, 0 ;[009]
|
||||
andi shift, 0xf9 ;[010]
|
||||
rxbit1: ;[ ]
|
||||
in x2, USBIN ;[011] <-- bit 1
|
||||
breq unstuff0 ;[012] *** unstuff escape
|
||||
andi x2, USBMASK ;[013] SE0 check for bit 1
|
||||
didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff
|
||||
breq se0 ;[014]
|
||||
eor r0, x2 ;[015]
|
||||
or phase, r0 ;[016]
|
||||
in r0, USBIN ;[017] <-- phase
|
||||
eor x1, x2 ;[018]
|
||||
bst x1, USBMINUS ;[019]
|
||||
bld shift, 1 ;[020]
|
||||
andi shift, 0xf3 ;[021]
|
||||
didUnstuff1: ;[ ]
|
||||
in x1, USBIN ;[022] <-- bit 2
|
||||
breq unstuff1 ;[023] *** unstuff escape
|
||||
eor r0, x1 ;[024]
|
||||
or phase, r0 ;[025]
|
||||
subi cnt, 1 ;[026] overflow check
|
||||
brcs overflow ;[027]
|
||||
in r0, USBIN ;[028] <-- phase
|
||||
eor x2, x1 ;[029]
|
||||
bst x2, USBMINUS ;[030]
|
||||
bld shift, 2 ;[031]
|
||||
andi shift, 0xe7 ;[032]
|
||||
didUnstuff2: ;[ ]
|
||||
in x2, USBIN ;[033] <-- bit 3
|
||||
breq unstuff2 ;[034] *** unstuff escape
|
||||
eor r0, x2 ;[035]
|
||||
or phase, r0 ;[036]
|
||||
eor x1, x2 ;[037]
|
||||
bst x1, USBMINUS ;[038]
|
||||
in r0, USBIN ;[039] <-- phase
|
||||
bld shift, 3 ;[040]
|
||||
andi shift, 0xcf ;[041]
|
||||
didUnstuff3: ;[ ]
|
||||
breq unstuff3 ;[042] *** unstuff escape
|
||||
nop ;[043]
|
||||
in x1, USBIN ;[044] <-- bit 4
|
||||
eor x2, x1 ;[045]
|
||||
bst x2, USBMINUS ;[046]
|
||||
bld shift, 4 ;[047]
|
||||
didUnstuff4: ;[ ]
|
||||
eor r0, x1 ;[048]
|
||||
or phase, r0 ;[049]
|
||||
in r0, USBIN ;[050] <-- phase
|
||||
andi shift, 0x9f ;[051]
|
||||
breq unstuff4 ;[052] *** unstuff escape
|
||||
rjmp continueWithBit5;[053]
|
||||
; [---] ;[054]
|
||||
|
||||
;----------------------------------------------------------------------------
|
||||
; Processing of received packet (numbers in brackets are cycles after center of SE0)
|
||||
;----------------------------------------------------------------------------
|
||||
;This is the only non-error exit point for the software receiver loop
|
||||
;we don't check any CRCs here because there is no time left.
|
||||
#define token x1
|
||||
se0:
|
||||
subi cnt, USB_BUFSIZE ;[5]
|
||||
neg cnt ;[6]
|
||||
cpi cnt, 3 ;[7]
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
|
||||
USB_STORE_PENDING(x2) ;[9] clear pending intr and check flag later. SE0 should be over.
|
||||
brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
|
||||
sub YL, cnt ;[11]
|
||||
sbci YH, 0 ;[12]
|
||||
ld token, y ;[13]
|
||||
cpi token, USBPID_DATA0 ;[15]
|
||||
breq handleData ;[16]
|
||||
cpi token, USBPID_DATA1 ;[17]
|
||||
breq handleData ;[18]
|
||||
ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
|
||||
mov x3, x2 ;[21] store for endpoint number
|
||||
andi x2, 0x7f ;[22] x2 is now ADDR
|
||||
lds shift, usbDeviceAddr;[23]
|
||||
cp x2, shift ;[25]
|
||||
overflow: ; This is a hack: brcs overflow will never have Z flag set
|
||||
brne ignorePacket ;[26] packet for different address
|
||||
cpi token, USBPID_IN ;[27]
|
||||
breq handleIn ;[28]
|
||||
cpi token, USBPID_SETUP ;[29]
|
||||
breq handleSetupOrOut ;[30]
|
||||
cpi token, USBPID_OUT ;[31]
|
||||
breq handleSetupOrOut ;[32]
|
||||
; rjmp ignorePacket ;fallthrough, should not happen anyway.
|
||||
|
||||
ignorePacket:
|
||||
clr shift
|
||||
sts usbCurrentTok, shift
|
||||
doReturn:
|
||||
pop cnt
|
||||
pop x4
|
||||
pop x3
|
||||
pop x2
|
||||
pop x1
|
||||
pop shift
|
||||
pop YH
|
||||
pop YL
|
||||
sofError:
|
||||
pop r0
|
||||
out SREG, r0
|
||||
pop r0
|
||||
reti
|
||||
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
handleIn3:
|
||||
lds cnt, usbTxLen3 ;[43]
|
||||
sbrc cnt, 4 ;[45]
|
||||
rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
|
||||
sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf3) ;[49]
|
||||
ldi YH, hi8(usbTxBuf3) ;[50]
|
||||
rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
|
||||
#endif
|
||||
|
||||
;Setup and Out are followed by a data packet two bit times (16 cycles) after
|
||||
;the end of SE0. The sync code allows up to 40 cycles delay from the start of
|
||||
;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
|
||||
handleSetupOrOut: ;[34]
|
||||
#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
|
||||
sbrc x3, 7 ;[34] skip if endpoint 0
|
||||
ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
|
||||
#endif
|
||||
sts usbCurrentTok, token;[36]
|
||||
pop cnt ;[38]
|
||||
pop x4 ;[40]
|
||||
pop x3 ;[42]
|
||||
pop x2 ;[44]
|
||||
pop x1 ;[46]
|
||||
pop shift ;[48]
|
||||
pop YH ;[50]
|
||||
pop YL ;[52]
|
||||
USB_LOAD_PENDING(r0) ;[54]
|
||||
sbrc r0, USB_INTR_PENDING_BIT;[55] check whether data is already arriving
|
||||
rjmp waitForJ ;[56] save the pops and pushes -- a new interrupt is aready pending
|
||||
rjmp sofError ;[57] not an error, but it does the pops and reti we want
|
||||
|
||||
|
||||
handleData:
|
||||
lds token, usbCurrentTok;[20]
|
||||
tst token ;[22]
|
||||
breq doReturn ;[23]
|
||||
lds x2, usbRxLen ;[24]
|
||||
tst x2 ;[26]
|
||||
brne sendNakAndReti ;[27]
|
||||
; 2006-03-11: The following two lines fix a problem where the device was not
|
||||
; recognized if usbPoll() was called less frequently than once every 4 ms.
|
||||
cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
|
||||
brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
|
||||
sts usbRxLen, cnt ;[30] store received data, swap buffers
|
||||
sts usbRxToken, token ;[32]
|
||||
lds x2, usbInputBufOffset;[34] swap buffers
|
||||
ldi cnt, USB_BUFSIZE ;[36]
|
||||
sub cnt, x2 ;[37]
|
||||
sts usbInputBufOffset, cnt;[38] buffers now swapped
|
||||
rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
|
||||
|
||||
handleIn:
|
||||
;We don't send any data as long as the C code has not processed the current
|
||||
;input data and potentially updated the output data. That's more efficient
|
||||
;in terms of code size than clearing the tx buffers when a packet is received.
|
||||
lds x1, usbRxLen ;[30]
|
||||
cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
|
||||
brge sendNakAndReti ;[33] unprocessed input packet?
|
||||
ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT
|
||||
sbrc x3, 7 ;[35] x3 contains addr + endpoint
|
||||
rjmp handleIn1 ;[36]
|
||||
#endif
|
||||
lds cnt, usbTxLen ;[37]
|
||||
sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
|
||||
sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf) ;[43]
|
||||
ldi YH, hi8(usbTxBuf) ;[44]
|
||||
rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
|
||||
|
||||
; Comment about when to set usbTxLen to USBPID_NAK:
|
||||
; We should set it back when we receive the ACK from the host. This would
|
||||
; be simple to implement: One static variable which stores whether the last
|
||||
; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
|
||||
; ACK. However, we set it back immediately when we send the package,
|
||||
; assuming that no error occurs and the host sends an ACK. We save one byte
|
||||
; RAM this way and avoid potential problems with endless retries. The rest of
|
||||
; the driver assumes error-free transfers anyway.
|
||||
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
|
||||
handleIn1: ;[38]
|
||||
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
|
||||
; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
|
||||
ldd x2, y+2 ;[38]
|
||||
sbrc x2, 0 ;[40]
|
||||
rjmp handleIn3 ;[41]
|
||||
#endif
|
||||
lds cnt, usbTxLen1 ;[42]
|
||||
sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
|
||||
rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
|
||||
sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
|
||||
ldi YL, lo8(usbTxBuf1) ;[48]
|
||||
ldi YH, hi8(usbTxBuf1) ;[49]
|
||||
rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
|
||||
#endif
|
||||
|
||||
|
||||
; USB spec says:
|
||||
; idle = J
|
||||
; J = (D+ = 0), (D- = 1)
|
||||
; K = (D+ = 1), (D- = 0)
|
||||
; Spec allows 7.5 bit times from EOP to SOP for replies
|
||||
|
||||
bitstuff7:
|
||||
eor x1, x4 ;[4]
|
||||
ldi x2, 0 ;[5]
|
||||
nop2 ;[6] C is zero (brcc)
|
||||
rjmp didStuff7 ;[8]
|
||||
|
||||
bitstuffN:
|
||||
eor x1, x4 ;[5]
|
||||
ldi x2, 0 ;[6]
|
||||
lpm ;[7] 3 cycle NOP, modifies r0
|
||||
out USBOUT, x1 ;[10] <-- out
|
||||
rjmp didStuffN ;[0]
|
||||
|
||||
#define bitStatus x3
|
||||
|
||||
sendNakAndReti:
|
||||
ldi cnt, USBPID_NAK ;[-19]
|
||||
rjmp sendCntAndReti ;[-18]
|
||||
sendAckAndReti:
|
||||
ldi cnt, USBPID_ACK ;[-17]
|
||||
sendCntAndReti:
|
||||
mov r0, cnt ;[-16]
|
||||
ldi YL, 0 ;[-15] R0 address is 0
|
||||
ldi YH, 0 ;[-14]
|
||||
ldi cnt, 2 ;[-13]
|
||||
; rjmp usbSendAndReti fallthrough
|
||||
|
||||
;usbSend:
|
||||
;pointer to data in 'Y'
|
||||
;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
|
||||
;uses: x1...x4, shift, cnt, Y
|
||||
;Numbers in brackets are time since first bit of sync pattern is sent
|
||||
usbSendAndReti: ; 12 cycles until SOP
|
||||
in x2, USBDDR ;[-12]
|
||||
ori x2, USBMASK ;[-11]
|
||||
sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
|
||||
in x1, USBOUT ;[-8] port mirror for tx loop
|
||||
out USBDDR, x2 ;[-7] <- acquire bus
|
||||
; need not init x2 (bitstuff history) because sync starts with 0
|
||||
ldi x4, USBMASK ;[-6] exor mask
|
||||
ldi shift, 0x80 ;[-5] sync byte is first byte sent
|
||||
ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes
|
||||
byteloop:
|
||||
bitloop:
|
||||
sbrs shift, 0 ;[8] [-3]
|
||||
eor x1, x4 ;[9] [-2]
|
||||
out USBOUT, x1 ;[10] [-1] <-- out
|
||||
ror shift ;[0]
|
||||
ror x2 ;[1]
|
||||
didStuffN:
|
||||
cpi x2, 0xfc ;[2]
|
||||
brcc bitstuffN ;[3]
|
||||
nop ;[4]
|
||||
subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37
|
||||
brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value
|
||||
sbrs shift, 0 ;[7]
|
||||
eor x1, x4 ;[8]
|
||||
ror shift ;[9]
|
||||
didStuff7:
|
||||
out USBOUT, x1 ;[10] <-- out
|
||||
ror x2 ;[0]
|
||||
cpi x2, 0xfc ;[1]
|
||||
brcc bitstuff7 ;[2]
|
||||
ld shift, y+ ;[3]
|
||||
dec cnt ;[5]
|
||||
brne byteloop ;[6]
|
||||
;make SE0:
|
||||
cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
|
||||
lds x2, usbNewDeviceAddr;[8]
|
||||
out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
|
||||
;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
||||
;set address only after data packet was sent, not after handshake
|
||||
subi YL, 2 ;[0]
|
||||
sbci YH, 0 ;[1]
|
||||
breq skipAddrAssign ;[2]
|
||||
sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
|
||||
skipAddrAssign:
|
||||
;end of usbDeviceAddress transfer
|
||||
ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
|
||||
USB_STORE_PENDING(x2) ;[5]
|
||||
ori x1, USBIDLE ;[6]
|
||||
in x2, USBDDR ;[7]
|
||||
cbr x2, USBMASK ;[8] set both pins to input
|
||||
mov x3, x1 ;[9]
|
||||
cbr x3, USBMASK ;[10] configure no pullup on both pins
|
||||
ldi x4, 4 ;[11]
|
||||
se0Delay:
|
||||
dec x4 ;[12] [15] [18] [21]
|
||||
brne se0Delay ;[13] [16] [19] [22]
|
||||
out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
|
||||
out USBDDR, x2 ;[24] <-- release bus now
|
||||
out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
|
||||
rjmp doReturn
|
||||
|
||||
Loading…
Reference in New Issue