mirror of https://github.com/raphnet/4nes4snes
473 lines
18 KiB
ArmAsm
473 lines
18 KiB
ArmAsm
/* Name: usbdrvasm16.S
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* Project: AVR USB driver
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* Author: Christian Starkjohann
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* Creation Date: 2007-06-15
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* Tabsize: 4
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* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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* License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
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* Revision: $Id: usbdrvasm16.S,v 1.1 2013-04-25 02:18:15 cvs Exp $
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*/
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/* Do not link this file! Link usbdrvasm.S instead, which includes the
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* appropriate implementation!
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*/
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/*
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General Description:
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This file is the 16 MHz version of the asssembler part of the USB driver. It
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requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
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oscillator).
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See usbdrv.h for a description of the entire driver.
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Since almost all of this code is timing critical, don't change unless you
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really know what you are doing! Many parts require not only a maximum number
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of CPU cycles, but even an exact number of cycles!
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*/
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;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
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;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
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; Numbers in brackets are clocks counted from center of last sync bit
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; when instruction starts
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USB_INTR_VECTOR:
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;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
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push YL ;[-25] push only what is necessary to sync with edge ASAP
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in YL, SREG ;[-23]
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push YL ;[-22]
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push YH ;[-20]
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;----------------------------------------------------------------------------
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; Synchronize with sync pattern:
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;----------------------------------------------------------------------------
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;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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;sync up with J to K edge during sync pattern -- use fastest possible loops
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;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
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waitForJ:
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sbis USBIN, USBMINUS ;[-18] wait for D- == 1
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rjmp waitForJ
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waitForK:
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;The following code results in a sampling window of < 1/4 bit which meets the spec.
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sbis USBIN, USBMINUS ;[-15]
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rjmp foundK ;[-14]
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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#if USB_COUNT_SOF
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lds YL, usbSofCount
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inc YL
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sts usbSofCount, YL
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#endif /* USB_COUNT_SOF */
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rjmp sofError
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foundK: ;[-12]
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;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
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;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
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;are cycles from center of first sync (double K) bit after the instruction
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push bitcnt ;[-12]
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; [---] ;[-11]
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lds YL, usbInputBufOffset;[-10]
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; [---] ;[-9]
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clr YH ;[-8]
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subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
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sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
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push shift ;[-5]
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; [---] ;[-4]
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ldi bitcnt, 0x55 ;[-3] [rx loop init]
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sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
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rjmp haveTwoBitsK ;[-1]
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pop shift ;[0] undo the push from before
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pop bitcnt ;[2] undo the push from before
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rjmp waitForK ;[4] this was not the end of sync, retry
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; The entire loop from waitForK until rjmp waitForK above must not exceed two
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; bit times (= 21 cycles).
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;----------------------------------------------------------------------------
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; push more registers and initialize values while we sample the first bits:
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;----------------------------------------------------------------------------
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haveTwoBitsK:
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push x1 ;[1]
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push x2 ;[3]
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push x3 ;[5]
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ldi shift, 0 ;[7]
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ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
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push x4 ;[9] == leap
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in x1, USBIN ;[11] <-- sample bit 0
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andi x1, USBMASK ;[12]
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bst x1, USBMINUS ;[13]
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bld shift, 7 ;[14]
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push cnt ;[15]
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ldi leap, 0 ;[17] [rx loop init]
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ldi cnt, USB_BUFSIZE;[18] [rx loop init]
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rjmp rxbit1 ;[19] arrives at [21]
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;----------------------------------------------------------------------------
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; Receiver loop (numbers in brackets are cycles within byte after instr)
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;----------------------------------------------------------------------------
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unstuff6:
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andi x2, USBMASK ;[03]
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ori x3, 1<<6 ;[04] will not be shifted any more
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andi shift, ~0x80;[05]
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mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
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subi leap, 3 ;[07] since this is a short (10 cycle) bit, enforce leap bit
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rjmp didUnstuff6 ;[08]
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unstuff7:
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ori x3, 1<<7 ;[09] will not be shifted any more
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in x2, USBIN ;[00] [10] re-sample bit 7
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andi x2, USBMASK ;[01]
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andi shift, ~0x80;[02]
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subi leap, 3 ;[03] since this is a short (10 cycle) bit, enforce leap bit
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rjmp didUnstuff7 ;[04]
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unstuffEven:
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ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
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in x1, USBIN ;[00] [10]
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andi shift, ~0x80;[01]
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andi x1, USBMASK ;[02]
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breq se0 ;[03]
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subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
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nop ;[05]
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rjmp didUnstuffE ;[06]
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unstuffOdd:
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ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
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in x2, USBIN ;[00] [10]
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andi shift, ~0x80;[01]
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andi x2, USBMASK ;[02]
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breq se0 ;[03]
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subi leap, 3 ;[04] since this is a short (10 cycle) bit, enforce leap bit
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nop ;[05]
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rjmp didUnstuffO ;[06]
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rxByteLoop:
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andi x1, USBMASK ;[03]
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eor x2, x1 ;[04]
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subi leap, 1 ;[05]
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brpl skipLeap ;[06]
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subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
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nop ;1
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skipLeap:
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subi x2, 1 ;[08]
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ror shift ;[09]
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didUnstuff6:
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cpi shift, 0xfc ;[10]
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in x2, USBIN ;[00] [11] <-- sample bit 7
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brcc unstuff6 ;[01]
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andi x2, USBMASK ;[02]
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eor x1, x2 ;[03]
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subi x1, 1 ;[04]
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ror shift ;[05]
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didUnstuff7:
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cpi shift, 0xfc ;[06]
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brcc unstuff7 ;[07]
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eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
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st y+, x3 ;[09] store data
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rxBitLoop:
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in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
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andi x1, USBMASK ;[01]
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eor x2, x1 ;[02]
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andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
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subi x2, 1 ;[04]
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ror shift ;[05]
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cpi shift, 0xfc ;[06]
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brcc unstuffEven ;[07]
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didUnstuffE:
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lsr x3 ;[08]
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lsr x3 ;[09]
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rxbit1:
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in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
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andi x2, USBMASK ;[01]
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breq se0 ;[02]
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eor x1, x2 ;[03]
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subi x1, 1 ;[04]
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ror shift ;[05]
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cpi shift, 0xfc ;[06]
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brcc unstuffOdd ;[07]
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didUnstuffO:
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subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
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brcs rxBitLoop ;[09]
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subi cnt, 1 ;[10]
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in x1, USBIN ;[00] [11] <-- sample bit 6
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brcc rxByteLoop ;[01]
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rjmp ignorePacket; overflow
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;----------------------------------------------------------------------------
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; Processing of received packet (numbers in brackets are cycles after center of SE0)
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;----------------------------------------------------------------------------
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;This is the only non-error exit point for the software receiver loop
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;we don't check any CRCs here because there is no time left.
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#define token x1
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se0:
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subi cnt, USB_BUFSIZE ;[5]
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neg cnt ;[6]
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cpi cnt, 3 ;[7]
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ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
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USB_STORE_PENDING(x2) ;[9] clear pending intr and check flag later. SE0 should be over.
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brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
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sub YL, cnt ;[11]
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sbci YH, 0 ;[12]
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ld token, y ;[13]
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cpi token, USBPID_DATA0 ;[15]
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breq handleData ;[16]
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cpi token, USBPID_DATA1 ;[17]
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breq handleData ;[18]
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ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
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mov x3, x2 ;[21] store for endpoint number
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andi x2, 0x7f ;[22] x2 is now ADDR
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lds shift, usbDeviceAddr;[23]
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cp x2, shift ;[25]
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overflow: ; This is a hack: brcs overflow will never have Z flag set
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brne ignorePacket ;[26] packet for different address
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cpi token, USBPID_IN ;[27]
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breq handleIn ;[28]
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cpi token, USBPID_SETUP ;[29]
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breq handleSetupOrOut ;[30]
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cpi token, USBPID_OUT ;[31]
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breq handleSetupOrOut ;[32]
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; rjmp ignorePacket ;fallthrough, should not happen anyway.
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ignorePacket:
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clr shift
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sts usbCurrentTok, shift
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doReturn:
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pop cnt
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pop x4
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pop x3
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pop x2
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pop x1
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pop shift
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pop bitcnt
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sofError:
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pop YH
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pop YL
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out SREG, YL
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pop YL
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reti
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;Setup and Out are followed by a data packet two bit times (16 cycles) after
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;the end of SE0. The sync code allows up to 40 cycles delay from the start of
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;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
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handleSetupOrOut: ;[34]
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#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
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sbrc x3, 7 ;[34] skip if endpoint 0
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ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
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#endif
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sts usbCurrentTok, token;[36]
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pop cnt ;[38]
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pop x4 ;[40]
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pop x3 ;[42]
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pop x2 ;[44]
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pop x1 ;[46]
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pop shift ;[48]
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pop bitcnt ;[50]
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USB_LOAD_PENDING(YL) ;[52]
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sbrc YL, USB_INTR_PENDING_BIT;[53] check whether data is already arriving
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rjmp waitForJ ;[54] save the pops and pushes -- a new interrupt is aready pending
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rjmp sofError ;[55] not an error, but it does the pops and reti we want
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handleData:
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lds token, usbCurrentTok;[20]
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tst token ;[22]
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breq doReturn ;[23]
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lds x2, usbRxLen ;[24]
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tst x2 ;[26]
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brne sendNakAndReti ;[27]
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; 2006-03-11: The following two lines fix a problem where the device was not
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; recognized if usbPoll() was called less frequently than once every 4 ms.
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cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
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brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
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sts usbRxLen, cnt ;[30] store received data, swap buffers
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sts usbRxToken, token ;[32]
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lds x2, usbInputBufOffset;[34] swap buffers
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ldi cnt, USB_BUFSIZE ;[36]
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sub cnt, x2 ;[37]
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sts usbInputBufOffset, cnt;[38] buffers now swapped
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rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
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handleIn:
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;We don't send any data as long as the C code has not processed the current
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;input data and potentially updated the output data. That's more efficient
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;in terms of code size than clearing the tx buffers when a packet is received.
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lds x1, usbRxLen ;[30]
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cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
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brge sendNakAndReti ;[33] unprocessed input packet?
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ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
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#if USB_CFG_HAVE_INTRIN_ENDPOINT
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sbrc x3, 7 ;[35] x3 contains addr + endpoint
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rjmp handleIn1 ;[36]
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#endif
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lds cnt, usbTxLen ;[37]
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sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
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rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
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sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
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ldi YL, lo8(usbTxBuf) ;[43]
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ldi YH, hi8(usbTxBuf) ;[44]
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rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
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; Comment about when to set usbTxLen to USBPID_NAK:
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; We should set it back when we receive the ACK from the host. This would
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; be simple to implement: One static variable which stores whether the last
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; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
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; ACK. However, we set it back immediately when we send the package,
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; assuming that no error occurs and the host sends an ACK. We save one byte
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; RAM this way and avoid potential problems with endless retries. The rest of
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; the driver assumes error-free transfers anyway.
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#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
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handleIn1: ;[38]
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#if USB_CFG_HAVE_INTRIN_ENDPOINT3
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; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
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ldd x2, y+2 ;[38]
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sbrc x2, 0 ;[40]
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rjmp handleIn3 ;[41]
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#endif
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lds cnt, usbTxLen1 ;[42]
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sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
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rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
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sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
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ldi YL, lo8(usbTxBuf1) ;[48]
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ldi YH, hi8(usbTxBuf1) ;[49]
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rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
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#endif
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#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
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handleIn3:
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lds cnt, usbTxLen3 ;[43]
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sbrc cnt, 4 ;[45]
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rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
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sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
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ldi YL, lo8(usbTxBuf3) ;[49]
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ldi YH, hi8(usbTxBuf3) ;[50]
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rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
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#endif
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; USB spec says:
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; idle = J
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; J = (D+ = 0), (D- = 1)
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; K = (D+ = 1), (D- = 0)
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; Spec allows 7.5 bit times from EOP to SOP for replies
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bitstuffN:
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eor x1, x4 ;[5]
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ldi x2, 0 ;[6]
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nop2 ;[7]
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nop ;[9]
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out USBOUT, x1 ;[10] <-- out
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rjmp didStuffN ;[0]
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bitstuff6:
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eor x1, x4 ;[4]
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ldi x2, 0 ;[5]
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nop2 ;[6] C is zero (brcc)
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rjmp didStuff6 ;[8]
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bitstuff7:
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eor x1, x4 ;[3]
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ldi x2, 0 ;[4]
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rjmp didStuff7 ;[5]
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sendNakAndReti:
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ldi x3, USBPID_NAK ;[-18]
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rjmp sendX3AndReti ;[-17]
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sendAckAndReti:
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ldi cnt, USBPID_ACK ;[-17]
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sendCntAndReti:
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mov x3, cnt ;[-16]
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sendX3AndReti:
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ldi YL, 20 ;[-15] x3==r20 address is 20
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ldi YH, 0 ;[-14]
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ldi cnt, 2 ;[-13]
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; rjmp usbSendAndReti fallthrough
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;usbSend:
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;pointer to data in 'Y'
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;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
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;uses: x1...x4, btcnt, shift, cnt, Y
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;Numbers in brackets are time since first bit of sync pattern is sent
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;We don't match the transfer rate exactly (don't insert leap cycles every third
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;byte) because the spec demands only 1.5% precision anyway.
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usbSendAndReti: ; 12 cycles until SOP
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in x2, USBDDR ;[-12]
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ori x2, USBMASK ;[-11]
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sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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in x1, USBOUT ;[-8] port mirror for tx loop
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out USBDDR, x2 ;[-7] <- acquire bus
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; need not init x2 (bitstuff history) because sync starts with 0
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ldi x4, USBMASK ;[-6] exor mask
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ldi shift, 0x80 ;[-5] sync byte is first byte sent
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txByteLoop:
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ldi bitcnt, 0x2a ;[-4] [6] binary 00101010
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txBitLoop:
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sbrs shift, 0 ;[-3] [7]
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eor x1, x4 ;[-2] [8]
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out USBOUT, x1 ;[-1] [9] <-- out N
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ror shift ;[0] [10]
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ror x2 ;[1]
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didStuffN:
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cpi x2, 0xfc ;[2]
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brcc bitstuffN ;[3]
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lsr bitcnt ;[4]
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brcc txBitLoop ;[5]
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brne txBitLoop ;[6]
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sbrs shift, 0 ;[7]
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eor x1, x4 ;[8]
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ror shift ;[9]
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didStuff6:
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out USBOUT, x1 ;[-1] [10] <-- out 6
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ror x2 ;[0] [11]
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cpi x2, 0xfc ;[1]
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brcc bitstuff6 ;[2]
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sbrs shift, 0 ;[3]
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eor x1, x4 ;[4]
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ror shift ;[5]
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ror x2 ;[6]
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didStuff7:
|
|
nop ;[7]
|
|
nop2 ;[8]
|
|
out USBOUT, x1 ;[-1][10] <-- out 7
|
|
cpi x2, 0xfc ;[0] [11]
|
|
brcc bitstuff7 ;[1]
|
|
ld shift, y+ ;[2]
|
|
dec cnt ;[4]
|
|
brne txByteLoop ;[4]
|
|
;make SE0:
|
|
cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
|
|
lds x2, usbNewDeviceAddr;[8]
|
|
out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
|
|
;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
|
;set address only after data packet was sent, not after handshake
|
|
subi YL, 2 ;[0]
|
|
sbci YH, 0 ;[1]
|
|
breq skipAddrAssign ;[2]
|
|
sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
|
|
skipAddrAssign:
|
|
;end of usbDeviceAddress transfer
|
|
ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
|
|
USB_STORE_PENDING(x2) ;[5]
|
|
ori x1, USBIDLE ;[6]
|
|
in x2, USBDDR ;[7]
|
|
cbr x2, USBMASK ;[8] set both pins to input
|
|
mov x3, x1 ;[9]
|
|
cbr x3, USBMASK ;[10] configure no pullup on both pins
|
|
ldi x4, 4 ;[11]
|
|
se0Delay:
|
|
dec x4 ;[12] [15] [18] [21]
|
|
brne se0Delay ;[13] [16] [19] [22]
|
|
out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
|
|
out USBDDR, x2 ;[24] <-- release bus now
|
|
out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
|
|
rjmp doReturn
|
|
|