implemented ultracic detection code
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Robin Jones
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b7dd066fa0
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166
inc/regsinternal.h
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166
inc/regsinternal.h
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@ -0,0 +1,166 @@
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//TODO: this file is actually part of the libdragon source and should be included from there!!!
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/**
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* @file regsinternal.h
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* @brief Register definitions for various hardware in the N64
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* @ingroup lowlevel
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*/
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#ifndef __LIBDRAGON_REGSINTERNAL_H
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#define __LIBDRAGON_REGSINTERNAL_H
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/**
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* @defgroup lowlevel Low Level Hardware Interfaces
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* @ingroup libdragon
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* @brief Low level hardware interface descriptions and functionality
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*
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* The low level hardware interfaces handle several functions in the N64 that
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* would otherwise be handled by a kernel or RTOS. This includes the @ref dma,
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* the @ref exceptions, the @ref interrupt and the @ref n64sys. The DMA controller
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* handles DMA requests between the cartridge and the N64 RDRAM. Other systems
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* in the N64 have their own DMA controllers that are handled in the relevant
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* subsystems. The exception handler traps any exceptions raised by the N64,
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* including the reset exception. The interrupt handler sets up the MIPS
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* interface (MI) which handles low level interrupt functionality for all other
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* systems in the N64. The N64 system interface provides the ability for code to
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* manipulate cache and boot options.
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*/
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/**
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* @brief Register definition for the AI interface
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* @ingroup lowlevel
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*/
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typedef struct AI_regs_s {
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/** @brief Pointer to uncached memory buffer of samples to play */
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volatile void * address;
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/** @brief Size in bytes of the buffer to be played. Should be
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* number of stereo samples * 2 * sizeof( uint16_t )
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*/
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uint32_t length;
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/** @brief DMA start register. Write a 1 to this register to start
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* playing back an audio sample. */
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uint32_t control;
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/** @brief AI status register. Bit 31 is the full bit, bit 30 is the busy bit. */
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uint32_t status;
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/** @brief Rate at which the buffer should be played.
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*
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* Use the following formula to calculate the value: ((2 * clockrate / frequency) + 1) / 2 - 1
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*/
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uint32_t dacrate;
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/** @brief The size of a single sample in bits. */
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uint32_t samplesize;
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} AI_regs_t;
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/**
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* @brief Register definition for the MI interface
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* @ingroup lowlevel
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*/
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typedef struct MI_regs_s {
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/** @brief Mode register */
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uint32_t mode;
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/** @brief Version register */
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uint32_t version;
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/** @brief Current interrupts on the system */
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uint32_t intr;
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/** @brief Interrupt mask */
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uint32_t mask;
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} MI_regs_t;
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/**
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* @brief Register definition for the VI interface
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* @ingroup lowlevel
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*/
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typedef struct VI_regs_s {
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/** @brief VI control register. Sets up various rasterization modes */
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uint32_t control;
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/** @brief Pointer to uncached buffer in memory to rasterize */
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void * framebuffer;
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/** @brief Width of the buffer in pixels */
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uint32_t width;
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/** @brief Vertical interrupt control register. Controls which horizontal
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* line must be hit to generate a VI interrupt
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*/
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uint32_t v_int;
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/** @brief Current vertical line counter. */
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uint32_t cur_line;
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/** @brief Timing generation register for PAL/NTSC signals */
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uint32_t timing;
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/** @brief Number of lines per frame */
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uint32_t v_sync;
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/** @brief Number of pixels in line and leap pattern */
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uint32_t h_sync;
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/** @brief Number of pixels in line, set identically to h_sync */
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uint32_t h_sync2;
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/** @brief Beginning and end of video horizontally */
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uint32_t h_limits;
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/** @brief Beginning and end of video vertically */
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uint32_t v_limits;
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/** @brief Beginning and end of color burst in vertical lines */
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uint32_t color_burst;
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/** @brief Horizontal scaling factor from buffer to screen */
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uint32_t h_scale;
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/** @brief Vertical scaling factor from buffer to screen */
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uint32_t v_scale;
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} VI_regs_t;
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/**
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* @brief Register definition for the PI interface
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* @ingroup lowlevel
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*/
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typedef struct PI_regs_s {
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/** @brief Uncached address in RAM where data should be found */
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volatile void * ram_address;
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/** @brief Address of data on peripheral */
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uint32_t pi_address;
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/** @brief How much data to read from RAM into the peripheral */
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uint32_t read_length;
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/** @brief How much data to write to RAM from the peripheral */
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uint32_t write_length;
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/** @brief Status of the PI, including DMA busy */
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uint32_t status;
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} PI_regs_t;
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/**
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* @brief Register definition for the SI interface
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* @ingroup lowlevel
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*/
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typedef struct SI_regs_s {
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/** @brief Uncached address in RAM where data should be found */
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volatile void * DRAM_addr;
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/** @brief Address to read when copying from PIF RAM */
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volatile void * PIF_addr_read;
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/** @brief Reserved word */
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uint32_t reserved1;
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/** @brief Reserved word */
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uint32_t reserved2;
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/** @brief Address to write when copying to PIF RAM */
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volatile void * PIF_addr_write;
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/** @brief Reserved word */
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uint32_t reserved3;
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/** @brief SI status, including DMA busy and IO busy */
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uint32_t status;
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} SI_regs_t;
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/**
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* @brief Register definition for the SP interface
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* @ingroup lowlevel
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*/
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typedef struct SP_regs_s {
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/** @brief RSP memory address (IMEM/DMEM) */
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volatile void * RSP_addr;
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/** @brief RDRAM memory address */
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volatile void * RDAM_addr;
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/** @brief RDRAM->RSP DMA length */
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uint32_t rsp_read_length;
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/** @brief RDP->RDRAM DMA length */
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uint32_t rsp_write_length;
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/** @brief RSP status */
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uint32_t status;
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/** @brief RSP DMA full */
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uint32_t rsp_dma_full;
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/** @brief RSP DMA busy */
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uint32_t rsp_dma_busy;
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/** @brief RSP Semaphore */
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uint32_t rsp_semaphore;
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} SP_regs_t;
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#endif
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97
src/cic.c
97
src/cic.c
@ -12,7 +12,13 @@
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//#include "si/cic.h"
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#include <stdint.h>
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#include <stddef.h>
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#include <string.h>
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#include <libdragon.h>
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#include "regsinternal.h"
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#include "cic.h"
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#include "types.h"
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#include "rom.h" //TODO: perhaps the pifram defines should be global
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// CIC seeds and status bits passed from PIF to IPL through PIF RAM
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@ -115,3 +121,94 @@ uint32_t si_crc32(const uint8_t *data, size_t size) {
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return c ^ 0xFFFFFFFF;
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}
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static volatile struct SI_regs_s * const SI_regs = (struct SI_regs_s *) 0xa4800000;
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static void * const PIF_RAM = (void *) 0x1fc007c0;
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/** @brief SI DMA busy */
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#define SI_STATUS_DMA_BUSY ( 1 << 0 )
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/** @brief SI IO busy */
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#define SI_STATUS_IO_BUSY ( 1 << 1 )
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static void __SI_DMA_wait(void) {
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while (SI_regs->status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY));
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}
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static void __controller_exec_PIF(void *inblock, void *outblock) {
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volatile uint64_t inblock_temp[8];
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volatile uint64_t outblock_temp[8];
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data_cache_hit_writeback_invalidate(inblock_temp, 64);
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memcpy(UncachedAddr(inblock_temp), inblock, 64);
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/* Be sure another thread doesn't get into a resource fight */
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disable_interrupts();
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__SI_DMA_wait();
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SI_regs->DRAM_addr = inblock_temp; // only cares about 23:0
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MEMORY_BARRIER();
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SI_regs->PIF_addr_write = PIF_RAM; // is it really ever anything else?
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MEMORY_BARRIER();
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__SI_DMA_wait();
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data_cache_hit_writeback_invalidate(outblock_temp, 64);
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SI_regs->DRAM_addr = outblock_temp;
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MEMORY_BARRIER();
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SI_regs->PIF_addr_read = PIF_RAM;
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MEMORY_BARRIER();
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__SI_DMA_wait();
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/* Now that we've copied, its safe to let other threads go */
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enable_interrupts();
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memcpy(outblock, UncachedAddr(outblock_temp), 64);
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}
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int pifram_x105_response_test() {
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static unsigned long long SI_eeprom_read_block[8] = {
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0xFFFFFFFFFFFFFFFF,
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0xFFFFFFFFFFFFFFFF,
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0xFFFFFFFFFFFFFFFF,
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0xFFFFFFFFFFFFFFFF,
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0xFFFFFFFFFFFFFFFF,
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0xFFFFFFFFFFFF0F0F,
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0x8B00620018000600,
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0x0100C000B0000002 //0x3f=02
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};
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static unsigned long long output[8];
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__controller_exec_PIF(SI_eeprom_read_block,output);
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/*
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expected result
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF 00 00
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3E C6 C0 4E BD 37 15 55
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5A 8C 2A 8C D3 71 71 00
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*/
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/* We are looking for 0x55 in [6], which
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* signifies that there is an x105 present.*/
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if( (output[6] & 0xFF) == 0x55 )
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{
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//x105 found!
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return 1;
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} else {
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//x105 not found!
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return 0;
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}
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}
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