mirror of https://github.com/raphnet/4nes4snes
581 lines
23 KiB
ArmAsm
581 lines
23 KiB
ArmAsm
/* Name: usbdrvasm165.S
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* Project: AVR USB driver
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* Author: Christian Starkjohann
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* Creation Date: 2007-04-22
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* Tabsize: 4
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* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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* License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
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* Revision: $Id: usbdrvasm165.S,v 1.1 2013-04-25 02:18:15 cvs Exp $
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*/
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/* Do not link this file! Link usbdrvasm.S instead, which includes the
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* appropriate implementation!
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*/
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/*
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General Description:
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This file is the 16.5 MHz version of the USB driver. It is intended for the
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ATTiny45 and similar controllers running on 16.5 MHz internal RC oscillator.
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This version contains a phase locked loop in the receiver routine to cope with
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slight clock rate deviations of up to +/- 1%.
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See usbdrv.h for a description of the entire driver.
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Since almost all of this code is timing critical, don't change unless you
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really know what you are doing! Many parts require not only a maximum number
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of CPU cycles, but even an exact number of cycles!
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*/
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;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
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;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
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;max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable
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;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes
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;nominal frequency: 16.5 MHz -> 11 cycles per bit
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; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%)
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; Numbers in brackets are clocks counted from center of last sync bit
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; when instruction starts
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USB_INTR_VECTOR:
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;order of registers pushed: r0, SREG [sofError], YL, YH, shift, x1, x2, x3, x4, cnt
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push r0 ;[-23] push only what is necessary to sync with edge ASAP
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in r0, SREG ;[-21]
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push r0 ;[-20]
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;----------------------------------------------------------------------------
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; Synchronize with sync pattern:
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;----------------------------------------------------------------------------
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;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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;sync up with J to K edge during sync pattern -- use fastest possible loops
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;first part has no timeout because it waits for IDLE or SE1 (== disconnected)
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waitForJ:
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sbis USBIN, USBMINUS ;[-18] wait for D- == 1
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rjmp waitForJ
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waitForK:
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;The following code results in a sampling window of < 1/4 bit which meets the spec.
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sbis USBIN, USBMINUS ;[-15]
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rjmp foundK ;[-14]
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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#if USB_COUNT_SOF
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lds YL, usbSofCount
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inc YL
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sts usbSofCount, YL
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#endif /* USB_COUNT_SOF */
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rjmp sofError
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foundK: ;[-12]
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;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
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;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
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;are cycles from center of first sync (double K) bit after the instruction
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push YL ;[-12]
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; [---] ;[-11]
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push YH ;[-10]
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; [---] ;[-9]
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lds YL, usbInputBufOffset;[-8]
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; [---] ;[-7]
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clr YH ;[-6]
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subi YL, lo8(-(usbRxBuf));[-5] [rx loop init]
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sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init]
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mov r0, x2 ;[-3] [rx loop init]
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sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
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rjmp haveTwoBitsK ;[-1]
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pop YH ;[0] undo the pushes from before
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pop YL ;[2]
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rjmp waitForK ;[4] this was not the end of sync, retry
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; The entire loop from waitForK until rjmp waitForK above must not exceed two
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; bit times (= 22 cycles).
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;----------------------------------------------------------------------------
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; push more registers and initialize values while we sample the first bits:
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;----------------------------------------------------------------------------
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haveTwoBitsK: ;[1]
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push shift ;[1]
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push x1 ;[3]
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push x2 ;[5]
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push x3 ;[7]
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ldi shift, 0xff ;[9] [rx loop init]
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ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag
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in x1, USBIN ;[11] <-- sample bit 0
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bst x1, USBMINUS ;[12]
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bld shift, 0 ;[13]
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push x4 ;[14] == phase
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; [---] ;[15]
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push cnt ;[16]
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; [---] ;[17]
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ldi phase, 0 ;[18] [rx loop init]
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ldi cnt, USB_BUFSIZE;[19] [rx loop init]
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rjmp rxbit1 ;[20]
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; [---] ;[21]
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;----------------------------------------------------------------------------
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; Receiver loop (numbers in brackets are cycles within byte after instr)
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;----------------------------------------------------------------------------
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/*
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byte oriented operations done during loop:
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bit 0: store data
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bit 1: SE0 check
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bit 2: overflow check
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bit 3: catch up
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bit 4: rjmp to achieve conditional jump range
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bit 5: PLL
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bit 6: catch up
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bit 7: jump, fixup bitstuff
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; 87 [+ 2] cycles
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------------------------------------------------------------------
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*/
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continueWithBit5:
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in x2, USBIN ;[055] <-- bit 5
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eor r0, x2 ;[056]
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or phase, r0 ;[057]
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sbrc phase, USBMINUS ;[058]
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lpm ;[059] optional nop3; modifies r0
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in phase, USBIN ;[060] <-- phase
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eor x1, x2 ;[061]
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bst x1, USBMINUS ;[062]
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bld shift, 5 ;[063]
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andi shift, 0x3f ;[064]
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in x1, USBIN ;[065] <-- bit 6
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breq unstuff5 ;[066] *** unstuff escape
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eor phase, x1 ;[067]
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eor x2, x1 ;[068]
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bst x2, USBMINUS ;[069]
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bld shift, 6 ;[070]
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didUnstuff6: ;[ ]
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in r0, USBIN ;[071] <-- phase
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cpi shift, 0x02 ;[072]
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brlo unstuff6 ;[073] *** unstuff escape
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didUnstuff5: ;[ ]
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nop2 ;[074]
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; [---] ;[075]
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in x2, USBIN ;[076] <-- bit 7
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eor x1, x2 ;[077]
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bst x1, USBMINUS ;[078]
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bld shift, 7 ;[079]
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didUnstuff7: ;[ ]
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eor r0, x2 ;[080]
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or phase, r0 ;[081]
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in r0, USBIN ;[082] <-- phase
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cpi shift, 0x04 ;[083]
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brsh rxLoop ;[084]
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; [---] ;[085]
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unstuff7: ;[ ]
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andi x3, ~0x80 ;[085]
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ori shift, 0x80 ;[086]
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in x2, USBIN ;[087] <-- sample stuffed bit 7
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nop ;[088]
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rjmp didUnstuff7 ;[089]
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; [---] ;[090]
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;[080]
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unstuff5: ;[067]
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eor phase, x1 ;[068]
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andi x3, ~0x20 ;[069]
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ori shift, 0x20 ;[070]
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in r0, USBIN ;[071] <-- phase
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mov x2, x1 ;[072]
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nop ;[073]
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nop2 ;[074]
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; [---] ;[075]
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in x1, USBIN ;[076] <-- bit 6
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eor r0, x1 ;[077]
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or phase, r0 ;[078]
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eor x2, x1 ;[079]
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bst x2, USBMINUS ;[080]
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bld shift, 6 ;[081] no need to check bitstuffing, we just had one
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in r0, USBIN ;[082] <-- phase
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rjmp didUnstuff5 ;[083]
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; [---] ;[084]
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;[074]
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unstuff6: ;[074]
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andi x3, ~0x40 ;[075]
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in x1, USBIN ;[076] <-- bit 6 again
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ori shift, 0x40 ;[077]
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nop2 ;[078]
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; [---] ;[079]
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rjmp didUnstuff6 ;[080]
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; [---] ;[081]
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;[071]
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unstuff0: ;[013]
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eor r0, x2 ;[014]
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or phase, r0 ;[015]
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andi x2, USBMASK ;[016] check for SE0
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in r0, USBIN ;[017] <-- phase
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breq didUnstuff0 ;[018] direct jump to se0 would be too long
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andi x3, ~0x01 ;[019]
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ori shift, 0x01 ;[020]
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mov x1, x2 ;[021] mov existing sample
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in x2, USBIN ;[022] <-- bit 1 again
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rjmp didUnstuff0 ;[023]
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; [---] ;[024]
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;[014]
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unstuff1: ;[024]
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eor r0, x1 ;[025]
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or phase, r0 ;[026]
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andi x3, ~0x02 ;[027]
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in r0, USBIN ;[028] <-- phase
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ori shift, 0x02 ;[029]
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mov x2, x1 ;[030]
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rjmp didUnstuff1 ;[031]
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; [---] ;[032]
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;[022]
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unstuff2: ;[035]
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eor r0, x2 ;[036]
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or phase, r0 ;[037]
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andi x3, ~0x04 ;[038]
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in r0, USBIN ;[039] <-- phase
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ori shift, 0x04 ;[040]
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mov x1, x2 ;[041]
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rjmp didUnstuff2 ;[042]
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; [---] ;[043]
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;[033]
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unstuff3: ;[043]
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in x2, USBIN ;[044] <-- bit 3 again
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eor r0, x2 ;[045]
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or phase, r0 ;[046]
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andi x3, ~0x08 ;[047]
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ori shift, 0x08 ;[048]
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nop ;[049]
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in r0, USBIN ;[050] <-- phase
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rjmp didUnstuff3 ;[051]
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; [---] ;[052]
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;[042]
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unstuff4: ;[053]
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andi x3, ~0x10 ;[054]
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in x1, USBIN ;[055] <-- bit 4 again
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ori shift, 0x10 ;[056]
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rjmp didUnstuff4 ;[057]
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; [---] ;[058]
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;[048]
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rxLoop: ;[085]
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eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others
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in x1, USBIN ;[000] <-- bit 0
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st y+, x3 ;[001]
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; [---] ;[002]
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eor r0, x1 ;[003]
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or phase, r0 ;[004]
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eor x2, x1 ;[005]
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in r0, USBIN ;[006] <-- phase
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ser x3 ;[007]
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bst x2, USBMINUS ;[008]
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bld shift, 0 ;[009]
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andi shift, 0xf9 ;[010]
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rxbit1: ;[ ]
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in x2, USBIN ;[011] <-- bit 1
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breq unstuff0 ;[012] *** unstuff escape
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andi x2, USBMASK ;[013] SE0 check for bit 1
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didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff
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breq se0 ;[014]
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eor r0, x2 ;[015]
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or phase, r0 ;[016]
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in r0, USBIN ;[017] <-- phase
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eor x1, x2 ;[018]
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bst x1, USBMINUS ;[019]
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bld shift, 1 ;[020]
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andi shift, 0xf3 ;[021]
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didUnstuff1: ;[ ]
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in x1, USBIN ;[022] <-- bit 2
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breq unstuff1 ;[023] *** unstuff escape
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eor r0, x1 ;[024]
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or phase, r0 ;[025]
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subi cnt, 1 ;[026] overflow check
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brcs overflow ;[027]
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in r0, USBIN ;[028] <-- phase
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eor x2, x1 ;[029]
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bst x2, USBMINUS ;[030]
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bld shift, 2 ;[031]
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andi shift, 0xe7 ;[032]
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didUnstuff2: ;[ ]
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in x2, USBIN ;[033] <-- bit 3
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breq unstuff2 ;[034] *** unstuff escape
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eor r0, x2 ;[035]
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or phase, r0 ;[036]
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eor x1, x2 ;[037]
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bst x1, USBMINUS ;[038]
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in r0, USBIN ;[039] <-- phase
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bld shift, 3 ;[040]
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andi shift, 0xcf ;[041]
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didUnstuff3: ;[ ]
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breq unstuff3 ;[042] *** unstuff escape
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nop ;[043]
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in x1, USBIN ;[044] <-- bit 4
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eor x2, x1 ;[045]
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bst x2, USBMINUS ;[046]
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bld shift, 4 ;[047]
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didUnstuff4: ;[ ]
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eor r0, x1 ;[048]
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or phase, r0 ;[049]
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in r0, USBIN ;[050] <-- phase
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andi shift, 0x9f ;[051]
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breq unstuff4 ;[052] *** unstuff escape
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rjmp continueWithBit5;[053]
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; [---] ;[054]
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;----------------------------------------------------------------------------
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; Processing of received packet (numbers in brackets are cycles after center of SE0)
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;----------------------------------------------------------------------------
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;This is the only non-error exit point for the software receiver loop
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;we don't check any CRCs here because there is no time left.
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#define token x1
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se0:
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subi cnt, USB_BUFSIZE ;[5]
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neg cnt ;[6]
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cpi cnt, 3 ;[7]
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ldi x2, 1<<USB_INTR_PENDING_BIT ;[8]
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USB_STORE_PENDING(x2) ;[9] clear pending intr and check flag later. SE0 should be over.
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brlo doReturn ;[10] this is probably an ACK, NAK or similar packet
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sub YL, cnt ;[11]
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sbci YH, 0 ;[12]
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ld token, y ;[13]
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cpi token, USBPID_DATA0 ;[15]
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breq handleData ;[16]
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cpi token, USBPID_DATA1 ;[17]
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breq handleData ;[18]
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ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
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mov x3, x2 ;[21] store for endpoint number
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andi x2, 0x7f ;[22] x2 is now ADDR
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lds shift, usbDeviceAddr;[23]
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cp x2, shift ;[25]
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overflow: ; This is a hack: brcs overflow will never have Z flag set
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brne ignorePacket ;[26] packet for different address
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cpi token, USBPID_IN ;[27]
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breq handleIn ;[28]
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cpi token, USBPID_SETUP ;[29]
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breq handleSetupOrOut ;[30]
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cpi token, USBPID_OUT ;[31]
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breq handleSetupOrOut ;[32]
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; rjmp ignorePacket ;fallthrough, should not happen anyway.
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ignorePacket:
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clr shift
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sts usbCurrentTok, shift
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doReturn:
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pop cnt
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pop x4
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pop x3
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pop x2
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pop x1
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pop shift
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pop YH
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pop YL
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sofError:
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pop r0
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out SREG, r0
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pop r0
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reti
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#if USB_CFG_HAVE_INTRIN_ENDPOINT && USB_CFG_HAVE_INTRIN_ENDPOINT3
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handleIn3:
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lds cnt, usbTxLen3 ;[43]
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sbrc cnt, 4 ;[45]
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rjmp sendCntAndReti ;[46] 48 + 16 = 64 until SOP
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sts usbTxLen3, x1 ;[47] x1 == USBPID_NAK from above
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ldi YL, lo8(usbTxBuf3) ;[49]
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ldi YH, hi8(usbTxBuf3) ;[50]
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rjmp usbSendAndReti ;[51] 53 + 12 = 65 until SOP
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#endif
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;Setup and Out are followed by a data packet two bit times (16 cycles) after
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;the end of SE0. The sync code allows up to 40 cycles delay from the start of
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;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
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handleSetupOrOut: ;[34]
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#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for second OUT endpoint, set usbCurrentTok to -1 */
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sbrc x3, 7 ;[34] skip if endpoint 0
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ldi token, -1 ;[35] indicate that this is endpoint 1 OUT
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#endif
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sts usbCurrentTok, token;[36]
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pop cnt ;[38]
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pop x4 ;[40]
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pop x3 ;[42]
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pop x2 ;[44]
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pop x1 ;[46]
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pop shift ;[48]
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pop YH ;[50]
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pop YL ;[52]
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USB_LOAD_PENDING(r0) ;[54]
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sbrc r0, USB_INTR_PENDING_BIT;[55] check whether data is already arriving
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rjmp waitForJ ;[56] save the pops and pushes -- a new interrupt is aready pending
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rjmp sofError ;[57] not an error, but it does the pops and reti we want
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handleData:
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lds token, usbCurrentTok;[20]
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tst token ;[22]
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breq doReturn ;[23]
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lds x2, usbRxLen ;[24]
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tst x2 ;[26]
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brne sendNakAndReti ;[27]
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; 2006-03-11: The following two lines fix a problem where the device was not
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; recognized if usbPoll() was called less frequently than once every 4 ms.
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cpi cnt, 4 ;[28] zero sized data packets are status phase only -- ignore and ack
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brmi sendAckAndReti ;[29] keep rx buffer clean -- we must not NAK next SETUP
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sts usbRxLen, cnt ;[30] store received data, swap buffers
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sts usbRxToken, token ;[32]
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lds x2, usbInputBufOffset;[34] swap buffers
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ldi cnt, USB_BUFSIZE ;[36]
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sub cnt, x2 ;[37]
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sts usbInputBufOffset, cnt;[38] buffers now swapped
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rjmp sendAckAndReti ;[40] 42 + 17 = 59 until SOP
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handleIn:
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;We don't send any data as long as the C code has not processed the current
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;input data and potentially updated the output data. That's more efficient
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;in terms of code size than clearing the tx buffers when a packet is received.
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lds x1, usbRxLen ;[30]
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cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
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brge sendNakAndReti ;[33] unprocessed input packet?
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ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
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#if USB_CFG_HAVE_INTRIN_ENDPOINT
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sbrc x3, 7 ;[35] x3 contains addr + endpoint
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rjmp handleIn1 ;[36]
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#endif
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lds cnt, usbTxLen ;[37]
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sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
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rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
|
|
sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
|
|
ldi YL, lo8(usbTxBuf) ;[43]
|
|
ldi YH, hi8(usbTxBuf) ;[44]
|
|
rjmp usbSendAndReti ;[45] 47 + 12 = 59 until SOP
|
|
|
|
; Comment about when to set usbTxLen to USBPID_NAK:
|
|
; We should set it back when we receive the ACK from the host. This would
|
|
; be simple to implement: One static variable which stores whether the last
|
|
; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
|
|
; ACK. However, we set it back immediately when we send the package,
|
|
; assuming that no error occurs and the host sends an ACK. We save one byte
|
|
; RAM this way and avoid potential problems with endless retries. The rest of
|
|
; the driver assumes error-free transfers anyway.
|
|
|
|
#if USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
|
|
handleIn1: ;[38]
|
|
#if USB_CFG_HAVE_INTRIN_ENDPOINT3
|
|
; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
|
|
ldd x2, y+2 ;[38]
|
|
sbrc x2, 0 ;[40]
|
|
rjmp handleIn3 ;[41]
|
|
#endif
|
|
lds cnt, usbTxLen1 ;[42]
|
|
sbrc cnt, 4 ;[44] all handshake tokens have bit 4 set
|
|
rjmp sendCntAndReti ;[45] 47 + 16 = 63 until SOP
|
|
sts usbTxLen1, x1 ;[46] x1 == USBPID_NAK from above
|
|
ldi YL, lo8(usbTxBuf1) ;[48]
|
|
ldi YH, hi8(usbTxBuf1) ;[49]
|
|
rjmp usbSendAndReti ;[50] 52 + 12 + 64 until SOP
|
|
#endif
|
|
|
|
|
|
; USB spec says:
|
|
; idle = J
|
|
; J = (D+ = 0), (D- = 1)
|
|
; K = (D+ = 1), (D- = 0)
|
|
; Spec allows 7.5 bit times from EOP to SOP for replies
|
|
|
|
bitstuff7:
|
|
eor x1, x4 ;[4]
|
|
ldi x2, 0 ;[5]
|
|
nop2 ;[6] C is zero (brcc)
|
|
rjmp didStuff7 ;[8]
|
|
|
|
bitstuffN:
|
|
eor x1, x4 ;[5]
|
|
ldi x2, 0 ;[6]
|
|
lpm ;[7] 3 cycle NOP, modifies r0
|
|
out USBOUT, x1 ;[10] <-- out
|
|
rjmp didStuffN ;[0]
|
|
|
|
#define bitStatus x3
|
|
|
|
sendNakAndReti:
|
|
ldi cnt, USBPID_NAK ;[-19]
|
|
rjmp sendCntAndReti ;[-18]
|
|
sendAckAndReti:
|
|
ldi cnt, USBPID_ACK ;[-17]
|
|
sendCntAndReti:
|
|
mov r0, cnt ;[-16]
|
|
ldi YL, 0 ;[-15] R0 address is 0
|
|
ldi YH, 0 ;[-14]
|
|
ldi cnt, 2 ;[-13]
|
|
; rjmp usbSendAndReti fallthrough
|
|
|
|
;usbSend:
|
|
;pointer to data in 'Y'
|
|
;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
|
|
;uses: x1...x4, shift, cnt, Y
|
|
;Numbers in brackets are time since first bit of sync pattern is sent
|
|
usbSendAndReti: ; 12 cycles until SOP
|
|
in x2, USBDDR ;[-12]
|
|
ori x2, USBMASK ;[-11]
|
|
sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
|
|
in x1, USBOUT ;[-8] port mirror for tx loop
|
|
out USBDDR, x2 ;[-7] <- acquire bus
|
|
; need not init x2 (bitstuff history) because sync starts with 0
|
|
ldi x4, USBMASK ;[-6] exor mask
|
|
ldi shift, 0x80 ;[-5] sync byte is first byte sent
|
|
ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes
|
|
byteloop:
|
|
bitloop:
|
|
sbrs shift, 0 ;[8] [-3]
|
|
eor x1, x4 ;[9] [-2]
|
|
out USBOUT, x1 ;[10] [-1] <-- out
|
|
ror shift ;[0]
|
|
ror x2 ;[1]
|
|
didStuffN:
|
|
cpi x2, 0xfc ;[2]
|
|
brcc bitstuffN ;[3]
|
|
nop ;[4]
|
|
subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37
|
|
brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value
|
|
sbrs shift, 0 ;[7]
|
|
eor x1, x4 ;[8]
|
|
ror shift ;[9]
|
|
didStuff7:
|
|
out USBOUT, x1 ;[10] <-- out
|
|
ror x2 ;[0]
|
|
cpi x2, 0xfc ;[1]
|
|
brcc bitstuff7 ;[2]
|
|
ld shift, y+ ;[3]
|
|
dec cnt ;[5]
|
|
brne byteloop ;[6]
|
|
;make SE0:
|
|
cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
|
|
lds x2, usbNewDeviceAddr;[8]
|
|
out USBOUT, x1 ;[10] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
|
|
;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
|
;set address only after data packet was sent, not after handshake
|
|
subi YL, 2 ;[0]
|
|
sbci YH, 0 ;[1]
|
|
breq skipAddrAssign ;[2]
|
|
sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
|
|
skipAddrAssign:
|
|
;end of usbDeviceAddress transfer
|
|
ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
|
|
USB_STORE_PENDING(x2) ;[5]
|
|
ori x1, USBIDLE ;[6]
|
|
in x2, USBDDR ;[7]
|
|
cbr x2, USBMASK ;[8] set both pins to input
|
|
mov x3, x1 ;[9]
|
|
cbr x3, USBMASK ;[10] configure no pullup on both pins
|
|
ldi x4, 4 ;[11]
|
|
se0Delay:
|
|
dec x4 ;[12] [15] [18] [21]
|
|
brne se0Delay ;[13] [16] [19] [22]
|
|
out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
|
|
out USBDDR, x2 ;[24] <-- release bus now
|
|
out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
|
|
rjmp doReturn
|
|
|