mirror of
https://xff.cz/git/pinephone-keyboard
synced 2024-12-22 12:58:48 -05:00
389 lines
8.2 KiB
C
389 lines
8.2 KiB
C
/**
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* Pinephone Keyboard Firmware
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*
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* Copyright (C) 2021 Ondřej Jirman <megi@xff.cz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include <em85f684a.h>
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#define BIT(n) (1u << (n))
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// we just use this interrupt for wakeup from sleep on input change
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void pinchange_interupt(void) __interrupt(IRQ_PINCHANGE)
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{
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// disable all input change interrupts
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P0_ICEN = BIT(5);
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}
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#define T0_SET_TIMEOUT(n) { \
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TL0 = 0x00; \
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TH0 = (0x10000u - n) >> 8; \
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TL0 = (0x10000u - n) & 0xff; \
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}
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#define delay_us(n) { \
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TL0 = 0x00; \
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TF0 = 0; \
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TH0 = (0x10000u - 2 * n) >> 8; \
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TL0 = (0x10000u - 2 * n) & 0xff; \
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while (!TF0); \
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}
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// Keyboard has 12 columns and 6 rows directly connected to GPIOs.
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//
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// C1 P95
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// C2 P96
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// C3 P97
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// C4 P50
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// C5 P51
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// C6 P52
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// C7 P53
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// C8 P54
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// C9 P55
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// C10 P56
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// C11 P57
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// C12 P80 (also USB IAP trigger when pulled low)
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//
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// R1 P60
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// R2 P61
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// R3 P62
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// R4 P63
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// R5 P64
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// R6 P65
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//
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// INT P90
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// SCL P92
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// SDA P93
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//
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// We will want to keep keyboard controller asleep unless some key is
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// pressed. If a key is pressed, the controller will continuously scan
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// for further pressed keys. When all keys are released, the controller
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// can go back to sleep.
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//
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// For this to work, we'll use port 6 ability to wake up the controller
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// on change.
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//
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// During sleep:
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// - all columns will be set to low state
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// - all rows will have pull-up enabled
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// - when user presses any key, row state will change to low and
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// the controller will wake up
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//
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// During active state:
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// - all columns will be put to hi-Z state, except for the currently
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// scanned one, which will be in low state
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// - state of rows will be read, and will indicate state of keys
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// in the selected column (0 = pressed, 1 = not pressed)
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//
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// De-bouncing:
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// - scanning will happen in 5ms intervals and only if the two
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// consecutive scans match, will the result be considered valid
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//
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// Configure GPIO for keyboard key scanning
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//
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// Switch to idle state
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//
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// In this state we can use keyscan_idle_is_pressed() to detect whether
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// any key is pressed, and switch to active mode via keyscan_active().
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//
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void keyscan_idle(void)
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{
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// enable output low on all columns (P9[7:5] P5[7:0] P8[0])
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PAGESW = 0;
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P5 = 0;
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P8 &= 0xfe;
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P9 &= 0x1f;
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P0_P5M0 = 0x00;
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P0_P8M0 &= 0xfe;
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PAGESW = 1;
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P1_P9M0 &= 0x1f;
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// enable input change interrupt on port6 and clear the flag
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P0_ICEN = BIT(5);
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ICIE = 1;
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}
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uint8_t keyscan_idle_is_pressed(void)
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{
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return ~P6 & 0x3f;
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}
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//
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// Switch to active mode.
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//
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// In this state, we can call keyscan_scan() to perform a scan.
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//
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void keyscan_active(void)
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{
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// put all columns to hi-Z (P9[7:5] P5[7:0] P8[0])
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// disable input change interrupt
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ICIE = 0;
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PAGESW = 0;
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P5 = 0;
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P8 &= 0xfe;
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P9 &= 0x1f;
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P0_P5M0 = ~0x00u;
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P0_P8M0 |= ~0xfeu;
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PAGESW = 1;
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P1_P9M0 |= ~0x1fu;
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}
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// XXX: we can debounce in the scan function too (3us?)
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// 12 byte storage required
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uint8_t keyscan_scan(uint8_t* res)
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{
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uint8_t pin, mask = 0, row;
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// for each column:
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// - output low on column
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// - wait (for voltage to stabilize)
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// - read rows
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// - turn column back to hi-Z
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PAGESW = 1;
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for (pin = 5; pin <= 7; pin++) {
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P1_P9M0 &= ~BIT(pin);
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delay_us(10);
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row = ~P6 & 0x3f;
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mask |= row;
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*res++ = row;
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P1_P9M0 |= BIT(pin);
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}
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PAGESW = 0;
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for (pin = 0; pin <= 7; pin++) {
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P0_P5M0 &= ~BIT(pin);
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delay_us(10);
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row = ~P6 & 0x3f;
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mask |= row;
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*res++ = row;
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P0_P5M0 |= BIT(pin);
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}
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P0_P8M0 &= ~BIT(0);
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delay_us(10);
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row = ~P6 & 0x3f;
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mask |= row;
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*res++ = row;
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P0_P8M0 |= BIT(0);
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return mask;
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}
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void ext_int_assert(void)
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{
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P90 = 0;
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PAGESW = 1;
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P1_P9M0 &= ~BIT(0);
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}
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void ext_int_deassert(void)
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{
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P90 = 0;
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PAGESW = 1;
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P1_P9M0 |= BIT(0);
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}
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#define I2C_N_REGS 16
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static uint8_t i2c_transfer = 0x00;
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static uint8_t i2c_addr = 0;
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static uint8_t i2c_regs[I2C_N_REGS] = {0xaa, 0x55};
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static uint8_t i2c_cmd[I2C_N_REGS];
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static uint8_t i2c_cmd_len = 0;
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static uint8_t go_boot = 0;
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void i2c_b_interupt(void) __interrupt(IRQ_I2CB)
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{
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uint8_t saved_page = PAGESW;
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uint8_t tmp;
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PAGESW = 0;
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// handle TX
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if (P0_I2CBINT & BIT(7)) {
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if (i2c_addr < 16)
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P0_I2CBDB = i2c_regs[i2c_addr++];
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else
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P0_I2CBDB = 0xff;
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P0_I2CBCR1 &= ~BIT(7); // clear data pending
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P0_I2CBINT &= ~BIT(7);
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}
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// handle RX
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if (P0_I2CBINT & BIT(6)) {
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tmp = P0_I2CBDB;
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if (i2c_cmd_len < 16)
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i2c_cmd[i2c_cmd_len++] = tmp;
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if (i2c_cmd_len) {
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if (i2c_cmd[0] == 0xa0)
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ext_int_assert();
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else if (i2c_cmd[0] == 0xa1)
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ext_int_deassert();
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else if (i2c_cmd[0] == 0xa2)
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go_boot = 1;
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}
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PAGESW = 0;
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P0_I2CBCR1 &= ~BIT(7); // clear data pending
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P0_I2CBINT &= ~BIT(6);
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}
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// handle stop condition
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if (P0_I2CBINT & BIT(4)) {
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i2c_addr = 0;
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i2c_cmd_len = 0;
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P0_I2CBINT &= ~BIT(4);
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}
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PAGESW = saved_page;
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}
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//
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// Slave mode I2C for communication with the SoC
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//
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// - address is 0x15
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// - 400kHz
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// - interrupts are used to handle tx/rx/end of transaction (stop bit)
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//
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void i2c_slave_init(void)
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{
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PAGESW = 0;
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// setup I2C B for slave mode
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//P0_I2CBCR1 = 0x20;
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//P0_I2CBCR2 = 0x07 << 1 | 0x01; // 400kHz mode, enable I2C B controller, enable
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P0_I2CBCR1 = 0x00;
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P0_I2CBCR2 = 0x07 << 1 | BIT(0); // 100kHz mode, enable I2C B controller, enable
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// setup I2C address
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P0_I2CBDAH = 0x00;
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P0_I2CBDAL = 0x15;
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P0_I2CBINT = BIT(5); // enable I2C B stop interrupt
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P0_EIE3 |= BIT(5); // enable I2C B interrupt
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}
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void main(void)
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{
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uint8_t scan_active = 0;
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PAGESW = 0;
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// setup interrupts
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EA = 0;
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IE = 0;
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P0_EIE1 = 0;
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P0_EIE2 = 0;
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P0_EIE3 = 0;
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// set CPU clock to normal (high frequency) mode
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// [7] = power down HS clock in low speed mode - 1: yes 0: no
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// [2:1] = high speed clock pre-divider - 1: /4 2: /2 3: /1
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// [0] = cpu clock mode 1: high speed mode 0: low speed mode
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CKCON1 = (CKCON1 & ~0x87u) | 0x07; // 0x87
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// set timer 1 and timer 0 clock source to sysclk/12 (2 MHz)
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CKCON0 = 0x00;
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// wait until high speed clock is stable
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while (!(CKCON0 & BIT(1)));
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// set both timers to 16-bit counter modes
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TMOD = 0x11;
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// timers clock is 2 MHz so we need to wait for 2000 ticks to get delay of 1ms
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//T0_SET_TIMEOUT(2000);
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// enable both timers
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TCON = 0x50;
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// setup watchdog (timer base is 8ms, prescaler sets up timeout /128 = ~1s)
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P0_WDTCR = 0x87; // enable watchdog ~1s
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P0_WDTKEY = 0x4e; // reset watchdog
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// P0_WDTCR = 0x07; // disable watchdog ~1s
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// P0_WDTKEY = 0xb1; // disable watchdog
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// power down unused peripherlas
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P0_DEVPD1 |= BIT(6) | BIT(5) | BIT(3) | BIT(1); // PWM A, timer 3, SPI, LVD
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P0_DEVPD2 |= BIT(6) | BIT(3) | BIT(0); // PWM C, PWM B, I2C A
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P0_DEVPD3 |= BIT(2) | BIT(1) | BIT(0); // PWM E, PWM D, PWM F
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// keep UART, SPI, and I2C A in reset
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//P0_PRST |= BIT(0) | BIT(2) | BIT(3);
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// enable pullups only all port 6 pins and make those pins into input
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PAGESW = 0;
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P0_PHCON0 = 0x00;
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P0_PHCON1 = 0xff; // port 6 pull-up enable
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P0_P6M0 = 0xff; // port 6 input
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PAGESW = 1;
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P1_PHCON2 = 0x00;
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// enable auto-tuning internal RC oscillator based on USB SOF packets
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//P1_IRCCTRL &= ~BIT(1); // disable manual trim
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i2c_slave_init();
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// enable interrupts
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EA = 1;
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ext_int_deassert();
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keyscan_idle();
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while (1) {
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if (go_boot) {
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EA = 0;
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__asm__("mov r6,#0x5a");
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__asm__("mov r7,#0xe7");
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__asm__("ljmp 0x0118");
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}
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if (scan_active) {
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uint8_t active_rows = keyscan_scan(i2c_regs + 4);
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if (!active_rows) {
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scan_active = 0;
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keyscan_idle();
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// power down
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//PCON |= BIT(1);
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//__asm__("nop");
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}
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continue;
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}
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if (keyscan_idle_is_pressed()) {
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scan_active = 1;
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keyscan_active();
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}
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}
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}
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