162 lines
5.8 KiB
C
162 lines
5.8 KiB
C
//
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// Copyright (c) 2017 The Altra64 project contributors
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// Portions (c) 2013 saturnu (Alt64) based on libdragon, Neo64Menu, ED64IO, libn64-hkz, libmikmod
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// See LICENSE file in the project root for full license information.
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//
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#ifndef _ROM_H
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#define _ROM_H
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/*
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*
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0000h (1 byte): initial PI_BSB_DOM1_LAT_REG value (0x80)
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0001h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x37)
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0002h (1 byte): initial PI_BSB_DOM1_PWD_REG value (0x12)
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0003h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x40)
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0004h - 0007h (1 dword): ClockRate
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0008h - 000Bh (1 dword): Program Counter (PC)
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000Ch - 000Fh (1 dword): Release
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0010h - 0013h (1 dword): CRC1
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0014h - 0017h (1 dword): CRC2
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0018h - 001Fh (2 dwords): Unknown (0x0000000000000000)
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0020h - 0033h (20 bytes): Image name
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Padded with 0x00 or spaces (0x20)
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0034h - 0037h (1 dword): Unknown (0x00000000)
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0038h - 003Bh (1 dword): Manufacturer ID
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0x0000004E = Nintendo ('N')
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003Ch - 003Dh (1 word): Cartridge ID
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003Eh - 003Fh (1 word): Country code
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0x4400 = Germany ('D')
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0x4500 = USA ('E')
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0x4A00 = Japan ('J')
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0x5000 = Europe ('P')
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0x5500 = Australia ('U')
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0040h - 0FFFh (1008 dwords): Boot code
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*/
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#define DP_BASE_REG 0x04100000
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#define VI_BASE_REG 0x04400000
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#define PI_BASE_REG 0x04600000
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#define PIF_RAM_START 0x1FC007C0
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/*
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* PI status register has 3 bits active when read from (PI_STATUS_REG - read)
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* Bit 0: DMA busy - set when DMA is in progress
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* Bit 1: IO busy - set when IO is in progress
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* Bit 2: Error - set when CPU issues IO request while DMA is busy
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*/
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#define PI_STATUS_REG (PI_BASE_REG+0x10)
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/* PI DRAM address (R/W): starting RDRAM address */
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#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
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/* PI pbus (cartridge) address (R/W): starting AD16 address */
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#define PI_CART_ADDR_REG (PI_BASE_REG+0x04)
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/* PI read length (R/W): read data length */
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#define PI_RD_LEN_REG (PI_BASE_REG+0x08)
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/* PI write length (R/W): write data length */
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#define PI_WR_LEN_REG (PI_BASE_REG+0x0C)
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/*
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* PI status (R): [0] DMA busy, [1] IO busy, [2], error
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* (W): [0] reset controller (and abort current op), [1] clear intr
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*/
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#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
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/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
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#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
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/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
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#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
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/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
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#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
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/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
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#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
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/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
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#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
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/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
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#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
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/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
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#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
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#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
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#define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG
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#define PI_STATUS_ERROR 0x04
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#define PI_STATUS_IO_BUSY 0x02
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#define PI_STATUS_DMA_BUSY 0x01
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#define DPC_START (DP_BASE_REG + 0x00)
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#define DPC_END (DP_BASE_REG + 0x04)
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#define DPC_CURRENT (DP_BASE_REG + 0x08)
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#define DPC_STATUS (DP_BASE_REG + 0x0C)
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#define DPC_CLOCK (DP_BASE_REG + 0x10)
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#define DPC_BUFBUSY (DP_BASE_REG + 0x14)
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#define DPC_PIPEBUSY (DP_BASE_REG + 0x18)
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#define DPC_TMEM (DP_BASE_REG + 0x1C)
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#define VI_CONTROL (VI_BASE_REG + 0x00)
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#define VI_FRAMEBUFFER (VI_BASE_REG + 0x04)
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#define VI_WIDTH (VI_BASE_REG + 0x08)
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#define VI_V_INT (VI_BASE_REG + 0x0C)
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#define VI_CUR_LINE (VI_BASE_REG + 0x10)
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#define VI_TIMING (VI_BASE_REG + 0x14)
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#define VI_V_SYNC (VI_BASE_REG + 0x18)
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#define VI_H_SYNC (VI_BASE_REG + 0x1C)
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#define VI_H_SYNC2 (VI_BASE_REG + 0x20)
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#define VI_H_LIMITS (VI_BASE_REG + 0x24)
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#define VI_COLOR_BURST (VI_BASE_REG + 0x28)
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#define VI_H_SCALE (VI_BASE_REG + 0x2C)
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#define VI_VSCALE (VI_BASE_REG + 0x30)
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#define PHYS_TO_K0(x) ((u32)(x)|0x80000000) /* physical to kseg0 */
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#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg0 to physical */
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#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
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#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg1 to physical */
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#define IO_READ(addr) (*(volatile u32*)PHYS_TO_K1(addr))
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#define IO_WRITE(addr,data) (*(volatile u32*)PHYS_TO_K1(addr)=(u32)(data))
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#define SAVE_SIZE_SRAM 32768
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#define SAVE_SIZE_SRAM96 131072 //TODO: or should this be 98304
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#define SAVE_SIZE_EEP4k 512
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#define SAVE_SIZE_EEP16k 2048
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#define SAVE_SIZE_FLASH 131072
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#define ROM_ADDR 0xb0000000
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#define FRAM_EXECUTE_CMD 0xD2000000
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#define FRAM_STATUS_MODE_CMD 0xE1000000
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#define FRAM_ERASE_OFFSET_CMD 0x4B000000
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#define FRAM_WRITE_OFFSET_CMD 0xA5000000
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#define FRAM_ERASE_MODE_CMD 0x78000000
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#define FRAM_WRITE_MODE_CMD 0xB4000000
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#define FRAM_READ_MODE_CMD 0xF0000000
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#define FRAM_STATUS_REG 0xA8000000
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#define FRAM_COMMAND_REG 0xA8010000
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//void romFill(...);
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void pif_boot();
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int is_valid_rom(unsigned char *buffer);
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void swap_header(unsigned char* header, int loadlength);
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u8 getCicType(u8 bios_cic);
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#endif
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