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Code Issues Releases Wiki Activity

Code refactoring

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This commit is contained in:
Robin Jones 2016-09-16 21:20:19 +01:00
parent 945331f92c
commit 6f771f166a
6 changed files with 349 additions and 303 deletions
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157
inc/rom.h Normal file
View File

@ -0,0 +1,157 @@
/*
*
0000h (1 byte): initial PI_BSB_DOM1_LAT_REG value (0x80)
0001h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x37)
0002h (1 byte): initial PI_BSB_DOM1_PWD_REG value (0x12)
0003h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x40)
0004h - 0007h (1 dword): ClockRate
0008h - 000Bh (1 dword): Program Counter (PC)
000Ch - 000Fh (1 dword): Release
0010h - 0013h (1 dword): CRC1
0014h - 0017h (1 dword): CRC2
0018h - 001Fh (2 dwords): Unknown (0x0000000000000000)
0020h - 0033h (20 bytes): Image name
Padded with 0x00 or spaces (0x20)
0034h - 0037h (1 dword): Unknown (0x00000000)
0038h - 003Bh (1 dword): Manufacturer ID
0x0000004E = Nintendo ('N')
003Ch - 003Dh (1 word): Cartridge ID
003Eh - 003Fh (1 word): Country code
0x4400 = Germany ('D')
0x4500 = USA ('E')
0x4A00 = Japan ('J')
0x5000 = Europe ('P')
0x5500 = Australia ('U')
0040h - 0FFFh (1008 dwords): Boot code
*/
#define DP_BASE_REG 0x04100000
#define VI_BASE_REG 0x04400000
#define PI_BASE_REG 0x04600000
#define PIF_RAM_START 0x1FC007C0
/*
* PI status register has 3 bits active when read from (PI_STATUS_REG - read)
* Bit 0: DMA busy - set when DMA is in progress
* Bit 1: IO busy - set when IO is in progress
* Bit 2: Error - set when CPU issues IO request while DMA is busy
*/
#define PI_STATUS_REG (PI_BASE_REG+0x10)
/* PI DRAM address (R/W): starting RDRAM address */
#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
/* PI pbus (cartridge) address (R/W): starting AD16 address */
#define PI_CART_ADDR_REG (PI_BASE_REG+0x04)
/* PI read length (R/W): read data length */
#define PI_RD_LEN_REG (PI_BASE_REG+0x08)
/* PI write length (R/W): write data length */
#define PI_WR_LEN_REG (PI_BASE_REG+0x0C)
/*
* PI status (R): [0] DMA busy, [1] IO busy, [2], error
* (W): [0] reset controller (and abort current op), [1] clear intr
*/
#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
#define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG
#define PI_STATUS_ERROR 0x04
#define PI_STATUS_IO_BUSY 0x02
#define PI_STATUS_DMA_BUSY 0x01
#define DPC_START (DP_BASE_REG + 0x00)
#define DPC_END (DP_BASE_REG + 0x04)
#define DPC_CURRENT (DP_BASE_REG + 0x08)
#define DPC_STATUS (DP_BASE_REG + 0x0C)
#define DPC_CLOCK (DP_BASE_REG + 0x10)
#define DPC_BUFBUSY (DP_BASE_REG + 0x14)
#define DPC_PIPEBUSY (DP_BASE_REG + 0x18)
#define DPC_TMEM (DP_BASE_REG + 0x1C)
#define VI_CONTROL (VI_BASE_REG + 0x00)
#define VI_FRAMEBUFFER (VI_BASE_REG + 0x04)
#define VI_WIDTH (VI_BASE_REG + 0x08)
#define VI_V_INT (VI_BASE_REG + 0x0C)
#define VI_CUR_LINE (VI_BASE_REG + 0x10)
#define VI_TIMING (VI_BASE_REG + 0x14)
#define VI_V_SYNC (VI_BASE_REG + 0x18)
#define VI_H_SYNC (VI_BASE_REG + 0x1C)
#define VI_H_SYNC2 (VI_BASE_REG + 0x20)
#define VI_H_LIMITS (VI_BASE_REG + 0x24)
#define VI_COLOR_BURST (VI_BASE_REG + 0x28)
#define VI_H_SCALE (VI_BASE_REG + 0x2C)
#define VI_VSCALE (VI_BASE_REG + 0x30)
#define PHYS_TO_K0(x) ((u32)(x)|0x80000000) /* physical to kseg0 */
#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg0 to physical */
#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg1 to physical */
#define IO_READ(addr) (*(volatile u32*)PHYS_TO_K1(addr))
#define IO_WRITE(addr,data) (*(volatile u32*)PHYS_TO_K1(addr)=(u32)(data))
#define SAVE_SIZE_SRAM 32768
#define SAVE_SIZE_SRAM128 131072
#define SAVE_SIZE_EEP4k 4096
#define SAVE_SIZE_EEP16k 16384
#define SAVE_SIZE_FLASH 131072
#define ROM_ADDR 0xb0000000
#define FRAM_EXECUTE_CMD 0xD2000000
#define FRAM_STATUS_MODE_CMD 0xE1000000
#define FRAM_ERASE_OFFSET_CMD 0x4B000000
#define FRAM_WRITE_OFFSET_CMD 0xA5000000
#define FRAM_ERASE_MODE_CMD 0x78000000
#define FRAM_WRITE_MODE_CMD 0xB4000000
#define FRAM_READ_MODE_CMD 0xF0000000
#define FRAM_STATUS_REG 0xA8000000
#define FRAM_COMMAND_REG 0xA8010000
#define CIC_6101 1
#define CIC_6102 2
#define CIC_6103 3
#define CIC_6104 4
#define CIC_6105 5
#define CIC_6106 6
//void romFill(...);
void pif_boot();
int is_valid_rom(unsigned char *buffer);
void swap_header(unsigned char* header, int loadlength);
u8 getCicType(u8 bios_cic);
int get_cic(unsigned char *buffer);

151
inc/utils.h
View File

@ -2,157 +2,13 @@
// rom tools - header inspect
#include <stdint.h>
#include <libdragon.h>
/*
*
0000h (1 byte): initial PI_BSB_DOM1_LAT_REG value (0x80)
0001h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x37)
0002h (1 byte): initial PI_BSB_DOM1_PWD_REG value (0x12)
0003h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x40)
0004h - 0007h (1 dword): ClockRate
0008h - 000Bh (1 dword): Program Counter (PC)
000Ch - 000Fh (1 dword): Release
0010h - 0013h (1 dword): CRC1
0014h - 0017h (1 dword): CRC2
0018h - 001Fh (2 dwords): Unknown (0x0000000000000000)
0020h - 0033h (20 bytes): Image name
Padded with 0x00 or spaces (0x20)
0034h - 0037h (1 dword): Unknown (0x00000000)
0038h - 003Bh (1 dword): Manufacturer ID
0x0000004E = Nintendo ('N')
003Ch - 003Dh (1 word): Cartridge ID
003Eh - 003Fh (1 word): Country code
0x4400 = Germany ('D')
0x4500 = USA ('E')
0x4A00 = Japan ('J')
0x5000 = Europe ('P')
0x5500 = Australia ('U')
0040h - 0FFFh (1008 dwords): Boot code
*/
#define DP_BASE_REG 0x04100000
#define VI_BASE_REG 0x04400000
#define PI_BASE_REG 0x04600000
#define PIF_RAM_START 0x1FC007C0
#include "rom.h"
/*
* PI status register has 3 bits active when read from (PI_STATUS_REG - read)
* Bit 0: DMA busy - set when DMA is in progress
* Bit 1: IO busy - set when IO is in progress
* Bit 2: Error - set when CPU issues IO request while DMA is busy
*/
#define PI_STATUS_REG (PI_BASE_REG+0x10)
/* PI DRAM address (R/W): starting RDRAM address */
#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
/* PI pbus (cartridge) address (R/W): starting AD16 address */
#define PI_CART_ADDR_REG (PI_BASE_REG+0x04)
/* PI read length (R/W): read data length */
#define PI_RD_LEN_REG (PI_BASE_REG+0x08)
/* PI write length (R/W): write data length */
#define PI_WR_LEN_REG (PI_BASE_REG+0x0C)
/*
* PI status (R): [0] DMA busy, [1] IO busy, [2], error
* (W): [0] reset controller (and abort current op), [1] clear intr
*/
#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
#define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG
#define PI_STATUS_ERROR 0x04
#define PI_STATUS_IO_BUSY 0x02
#define PI_STATUS_DMA_BUSY 0x01
#define DPC_START (DP_BASE_REG + 0x00)
#define DPC_END (DP_BASE_REG + 0x04)
#define DPC_CURRENT (DP_BASE_REG + 0x08)
#define DPC_STATUS (DP_BASE_REG + 0x0C)
#define DPC_CLOCK (DP_BASE_REG + 0x10)
#define DPC_BUFBUSY (DP_BASE_REG + 0x14)
#define DPC_PIPEBUSY (DP_BASE_REG + 0x18)
#define DPC_TMEM (DP_BASE_REG + 0x1C)
#define VI_CONTROL (VI_BASE_REG + 0x00)
#define VI_FRAMEBUFFER (VI_BASE_REG + 0x04)
#define VI_WIDTH (VI_BASE_REG + 0x08)
#define VI_V_INT (VI_BASE_REG + 0x0C)
#define VI_CUR_LINE (VI_BASE_REG + 0x10)
#define VI_TIMING (VI_BASE_REG + 0x14)
#define VI_V_SYNC (VI_BASE_REG + 0x18)
#define VI_H_SYNC (VI_BASE_REG + 0x1C)
#define VI_H_SYNC2 (VI_BASE_REG + 0x20)
#define VI_H_LIMITS (VI_BASE_REG + 0x24)
#define VI_COLOR_BURST (VI_BASE_REG + 0x28)
#define VI_H_SCALE (VI_BASE_REG + 0x2C)
#define VI_VSCALE (VI_BASE_REG + 0x30)
#define PHYS_TO_K0(x) ((u32)(x)|0x80000000) /* physical to kseg0 */
#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg0 to physical */
#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg1 to physical */
#define IO_READ(addr) (*(volatile u32*)PHYS_TO_K1(addr))
#define IO_WRITE(addr,data) (*(volatile u32*)PHYS_TO_K1(addr)=(u32)(data))
#define SAVE_SIZE_SRAM 32768
#define SAVE_SIZE_SRAM128 131072
#define SAVE_SIZE_EEP4k 4096
#define SAVE_SIZE_EEP16k 16384
#define SAVE_SIZE_FLASH 131072
#define ROM_ADDR 0xb0000000
#define FRAM_EXECUTE_CMD 0xD2000000
#define FRAM_STATUS_MODE_CMD 0xE1000000
#define FRAM_ERASE_OFFSET_CMD 0x4B000000
#define FRAM_WRITE_OFFSET_CMD 0xA5000000
#define FRAM_ERASE_MODE_CMD 0x78000000
#define FRAM_WRITE_MODE_CMD 0xB4000000
#define FRAM_READ_MODE_CMD 0xF0000000
#define FRAM_STATUS_REG 0xA8000000
#define FRAM_COMMAND_REG 0xA8010000
#define CIC_6101 1
#define CIC_6102 2
#define CIC_6103 3
#define CIC_6104 4
#define CIC_6105 5
#define CIC_6106 6
#if !defined(MIN)
#define MIN(a, b) ({ \
__typeof__ (a) _a = (a); \
@ -178,16 +34,13 @@ void _data_cache_invalidate_all(void);
void printText(char *msg, int x, int y, display_context_t dcon);
// End ...
int is_valid_rom(unsigned char *buffer);
void swap_header(unsigned char* header, int loadlength);
void restoreTiming(void);
void simulate_boot(u32 boot_cic, u8 bios_cic, u32 *cheat_list[2]);
u8 getCicType(u8 bios_cic);
int get_cic(unsigned char *buffer);
int get_cic_save(char *cartid, int *cic, int *save);
//const char* saveTypeToExtension(int type);
const char* saveTypeToExtension(int type, int etype);

98
src/menu.c
View File

@ -2551,7 +2551,9 @@ void alterRomConfig(int type, int mode){
u8 min_country=0;
u8 max_country=2;
if(type==1){//start cic
switch (type) {
case 1:
//start cic
if(mode==1){
//down
if(rom_config[1]<max_cic)
@ -2566,8 +2568,10 @@ void alterRomConfig(int type, int mode){
if(rom_config[1]==3)
rom_config[1]--;
}
}//end cic
else if(type==2){//start save
//end cic
break;
case 2:
//start save
if(mode==1){
//down
if(rom_config[2]<max_save)
@ -2578,8 +2582,10 @@ void alterRomConfig(int type, int mode){
if(rom_config[2]>min_save)
rom_config[2]--;
}
}//end save
else if(type==3){//start tv
//end save
break;
case 3:
//start tv
if(mode==1){
//down
if(rom_config[3]<max_tv)
@ -2590,8 +2596,10 @@ void alterRomConfig(int type, int mode){
if(rom_config[3]>min_tv)
rom_config[3]--;
}
}//end tv
else if(type==4){//start cheat
//end tv
break;
case 4:
//start cheat
if(mode==1){
//down
if(rom_config[4]<max_cheat)
@ -2602,8 +2610,10 @@ void alterRomConfig(int type, int mode){
if(rom_config[4]>min_cheat)
rom_config[4]--;
}
}//end cheat
else if(type==5){//start chk sum
//end cheat
break;
case 5:
//start chk sum
if(mode==1){
//down
if(rom_config[5]<max_chk_sum)
@ -2614,8 +2624,10 @@ void alterRomConfig(int type, int mode){
if(rom_config[5]>min_chk_sum)
rom_config[5]--;
}
}//end chk sum
else if(type==6){ //start quality
//end chk sum
break;
case 6:
//start quality
if(mode==1){
//down
if(rom_config[6]<max_quality)
@ -2626,8 +2638,9 @@ void alterRomConfig(int type, int mode){
if(rom_config[6]>min_quality)
rom_config[6]--;
}
}
else if(type==7){ //start country
break;
case 7:
//start country
if(mode==1){
//down
if(rom_config[7]<max_country)
@ -2638,6 +2651,7 @@ void alterRomConfig(int type, int mode){
if(rom_config[7]>min_country)
rom_config[7]--;
}
break;
}
}
@ -3137,7 +3151,8 @@ int main(void) {
struct controller_data keys_held = get_keys_held();
if(keys.c[0].up || keys_held.c[0].up || keys_held.c[0].y > +25) {
if(input_mapping==1){
switch (input_mapping) {
case 1:
if(select_mode){
if(count!=0){
if(scroll_behaviour==1)
@ -3163,14 +3178,14 @@ int main(void) {
display_show(disp);
}
}
}
else if(input_mapping==2){
}
else if(input_mapping==3){
break;
case 2:
break;
case 3:
//chr input screen
set=1;
}
else if(input_mapping==7){
break;
case 7:
while( !(disp = display_lock()) );
new_scroll_pos(&cursor, &page, MAX_LIST, count);
@ -3181,8 +3196,8 @@ int main(void) {
display_show(disp);
input_mapping=7;
sleep(80);
}
else if(input_mapping==8){
break;
case 8:
while( !(disp = display_lock()) );
drawBg(disp); //background
@ -3191,11 +3206,13 @@ int main(void) {
display_show(disp);
input_mapping=8;
sleep(80);
break;
}
}
if(keys.c[0].down || keys_held.c[0].down || keys_held.c[0].y < -25) {
if(input_mapping==1){
switch (input_mapping) {
case 1:
if(select_mode){
if(count!=0){
if(scroll_behaviour==1)
@ -3219,14 +3236,14 @@ int main(void) {
display_show(disp);
}
}
}
else if(input_mapping==2){
}
else if(input_mapping==3){
break;
case 2:
break;
case 3:
//chr input screen
set=3;
}
else if(input_mapping==7){
break;
case 7:
while( !(disp = display_lock()) );
new_scroll_pos(&cursor, &page, MAX_LIST, count);
@ -3239,8 +3256,8 @@ int main(void) {
display_show(disp);
input_mapping=7;
sleep(80);
}
else if(input_mapping==8){
break;
case 8:
while( !(disp = display_lock()) );
drawBg(disp);
@ -3249,10 +3266,12 @@ int main(void) {
display_show(disp);
input_mapping=8;
sleep(80);
break;
}
}
else if(keys.c[0].left || keys_held.c[0].left || keys_held.c[0].x < -25) {
if(input_mapping==1){
switch (input_mapping) {
case 1:
if(select_mode){
if(count!=0 && scroll_behaviour==0 && cursor-20>=0){
page-=20;
@ -3267,14 +3286,14 @@ int main(void) {
display_show(disp);
}
}
else if(input_mapping==2){
}
else if(input_mapping==3){
break;
case 2:
break;
case 3:
//chr input screen
set=4;
}
else if(input_mapping==7){
break;
case 7:
while( !(disp = display_lock()) );
new_scroll_pos(&cursor, &page, MAX_LIST, count);
@ -3287,6 +3306,7 @@ int main(void) {
display_show(disp);
input_mapping=7;
sleep(80);
break;
}
}
else if(keys.c[0].right || keys_held.c[0].right || keys_held.c[0].x > +25) {
@ -3908,7 +3928,7 @@ int main(void) {
drawBoxNumber(disp,2);
display_show(disp);
printText("ALT64: v0.1.8.6.1", 9, 8, disp);
printText("ALT64: v0.1.8.6.1.1", 9, 8, disp);
printText(" ", 9, -1, disp);
printText("by Saturnu", 9, -1, disp);
printText("& JonesAlmighty", 9, -1, disp);

94
src/rom.c Normal file
View File

@ -0,0 +1,94 @@
#include "sram.h"
#include "everdrive.h"
#include "sys.h"
void pif_boot()
{
//TODO: implement
}
int is_valid_rom(unsigned char *buffer) {
/* Test if rom is a native .z64 image with header 0x80371240. [ABCD] */
if((buffer[0]==0x80)&&(buffer[1]==0x37)&&(buffer[2]==0x12)&&(buffer[3]==0x40))
return 0;
/* Test if rom is a byteswapped .v64 image with header 0x37804012. [BADC] */
else if((buffer[0]==0x37)&&(buffer[1]==0x80)&&(buffer[2]==0x40)&&(buffer[3]==0x12))
return 1;
/* Test if rom is a wordswapped .n64 image with header 0x40123780. [DCBA] */
else if((buffer[0]==0x40)&&(buffer[1]==0x12)&&(buffer[2]==0x37)&&(buffer[3]==0x80))
return 2;
else
return 0;
}
void swap_header(unsigned char* header, int loadlength) {
unsigned char temp;
int i;
/* Btyeswap if .v64 image. */
if( header[0]==0x37) {
for (i = 0; i < loadlength; i+=2) {
temp= header[i];
header[i]= header[i+1];
header[i+1]=temp;
}
}
/* Wordswap if .n64 image. */
else if( header[0]==0x40) {
for (i = 0; i < loadlength; i+=4) {
temp= header[i];
header[i]= header[i+3];
header[i+3]=temp;
temp= header[i+1];
header[i+1]= header[i+2];
header[i+2]=temp;
}
}
}
u8 getCicType(u8 bios_cic) {
u8 cic_buff[2048];
volatile u8 cic_chip;
volatile u32 val;
if (bios_cic) {
evd_setCfgBit(ED_CFG_SDRAM_ON, 0);
sleep(10);
val = *(u32 *) 0xB0000170;
dma_read_s(cic_buff, 0xB0000040, 1024);
cic_chip = get_cic(cic_buff);
evd_setCfgBit(ED_CFG_SDRAM_ON, 1);
sleep(10);
}
else {
val = *(u32 *) 0xB0000170;
dma_read_s(cic_buff, 0xB0000040, 1024);
cic_chip = get_cic(cic_buff);
}
return cic_chip;
}
int get_cic(unsigned char *buffer) {
unsigned int crc;
// figure out the CIC
crc = CRC_Calculate(0, buffer, 1000);
switch(crc) {
case 0x303faac9:
case 0xf0da3d50:
return 1;
case 0xf3106101:
return 2;
case 0xe7cd9d51:
return 3;
case 0x7ae65c9:
return 5;
case 0x86015f8f:
return 6;
}
return 2;
}

58
src/usb.c
View File

@ -1,49 +1,49 @@
//#include "everdrive.h"
//#include "sys.h"
//#include "types.h"
//#include <libdragon.h>
//#include "rom.h"
#include "everdrive.h"
#include "sys.h"
#include "types.h"
#include <libdragon.h>
#include "rom.h"
//u8 cmdTest();
//u8 cmdFill();
//u8 cmdReadRom();
//u8 cmdWriteRom();
u8 cmdTest();
u8 cmdFill();
u8 cmdReadRom();
u8 cmdWriteRom();
//u64 usb_buff[128];
//u8 *usb_buff8; // = (u8 *) usb_buff;
u64 usb_buff[128];
u8 *usb_buff8; // = (u8 *) usb_buff;
//#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
//#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
//#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
//#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
//#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
//#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
//#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
//#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
//#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
//#define IO_WRITE(addr,data) (*(volatile u32*)PHYS_TO_K1(addr)=(u32)(data))
//#define PI_BASE_REG 0x04600000
#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
#define IO_WRITE(addr,data) (*(volatile u32*)PHYS_TO_K1(addr)=(u32)(data))
#define PI_BASE_REG 0x04600000
//extern u8 system_cic;
extern u8 system_cic;
/*u8 usbListener() {
u8 usbListener() {
volatile u16 resp;
volatile u8 cmd;
@ -83,12 +83,17 @@
//IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x0c);
//IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x80);
//evdSetESaveType(SAVE_TYPE_EEP16k);
system_cic = CIC_6102;
//system_cic = CIC_6102; //TODO: re-enable
evd_lockRegs();
IO_WRITE(PI_STATUS_REG, 3);
sleep(2);
pif_boot();
break;
case 'D':
//TODO: initiate debug session
break;
default:
break;
}
@ -117,7 +122,7 @@ u8 cmdFill() {
usb_buff8[i] = 0;
}
//console_printf("buff prepared\n");
romFill(0, 0x200000, 0);
//romFill(0, 0x200000, 0); //TODO: re-enable
//console_printf("fill done\n");
usb_buff8[3] = 'k';
@ -178,4 +183,3 @@ u8 cmdWriteRom() {
return 0;
}
*/

94
src/utils.c
View File

@ -23,89 +23,7 @@ extern short int boot_country;
static u8 __attribute__((aligned(16))) dmaBuf[128*1024];
static volatile struct _PI_regs_s * const _PI_regs = (struct _PI_regs_s *)0xa4600000;
int is_valid_rom(unsigned char *buffer) {
/* Test if rom is a native .z64 image with header 0x80371240. [ABCD] */
if((buffer[0]==0x80)&&(buffer[1]==0x37)&&(buffer[2]==0x12)&&(buffer[3]==0x40))
return 0;
/* Test if rom is a byteswapped .v64 image with header 0x37804012. [BADC] */
else if((buffer[0]==0x37)&&(buffer[1]==0x80)&&(buffer[2]==0x40)&&(buffer[3]==0x12))
return 1;
/* Test if rom is a wordswapped .n64 image with header 0x40123780. [DCBA] */
else if((buffer[0]==0x40)&&(buffer[1]==0x12)&&(buffer[2]==0x37)&&(buffer[3]==0x80))
return 2;
else
return 0;
}
void swap_header(unsigned char* header, int loadlength) {
unsigned char temp;
int i;
/* Btyeswap if .v64 image. */
if( header[0]==0x37) {
for (i = 0; i < loadlength; i+=2) {
temp= header[i];
header[i]= header[i+1];
header[i+1]=temp;
}
}
/* Wordswap if .n64 image. */
else if( header[0]==0x40) {
for (i = 0; i < loadlength; i+=4) {
temp= header[i];
header[i]= header[i+3];
header[i+3]=temp;
temp= header[i+1];
header[i+1]= header[i+2];
header[i+2]=temp;
}
}
}
u8 getCicType(u8 bios_cic) {
u8 cic_buff[2048];
volatile u8 cic_chip;
volatile u32 val;
if (bios_cic) {
evd_setCfgBit(ED_CFG_SDRAM_ON, 0);
sleep(10);
val = *(u32 *) 0xB0000170;
dma_read_s(cic_buff, 0xB0000040, 1024);
cic_chip = get_cic(cic_buff);
evd_setCfgBit(ED_CFG_SDRAM_ON, 1);
sleep(10);
}
else {
val = *(u32 *) 0xB0000170;
dma_read_s(cic_buff, 0xB0000040, 1024);
cic_chip = get_cic(cic_buff);
}
return cic_chip;
}
int get_cic(unsigned char *buffer) {
unsigned int crc;
// figure out the CIC
crc = CRC_Calculate(0, buffer, 1000);
switch(crc) {
case 0x303faac9:
case 0xf0da3d50:
return 1;
case 0xf3106101:
return 2;
case 0xe7cd9d51:
return 3;
case 0x7ae65c9:
return 5;
case 0x86015f8f:
return 6;
}
return 2;
}
int get_cic_save(char *cartid, int *cic, int *save) {
// variables
@ -699,12 +617,12 @@ void drawImage(display_context_t dcon, sprite_t *sprite) {
}
#define CIC_6101 1
#define CIC_6102 2
#define CIC_6103 3
#define CIC_6104 4
#define CIC_6105 5
#define CIC_6106 6
//#define CIC_6101 1
//#define CIC_6102 2
//#define CIC_6103 3
//#define CIC_6104 4
//#define CIC_6105 5
//#define CIC_6106 6
#define ROM ((vu32 *)0xB0000000)
#define EXE_START 0xB0001000