mirror of
https://github.com/raphnet/gc_n64_usb-v3
synced 2024-12-22 07:18:52 -05:00
253 lines
4.9 KiB
ArmAsm
253 lines
4.9 KiB
ArmAsm
#include <avr/io.h>
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.text
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.global gcn64_sendBytes
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.global gcn64_receiveBytes
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#define xl r26
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#define xh r27
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#define yl r28
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#define yh r29
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#define zl r30
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#define zh r31
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#define __zero_reg__ r1
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/* the value of the gpio is pre-configured to low. We simulate
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an open drain output by toggling the direction */
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#ifdef STK525
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#define GCN64_DATA_PORT _SFR_IO_ADDR(PORTA)
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#define GCN64_DATA_DDR _SFR_IO_ADDR(DDRA)
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#define GCN64_DATA_PIN _SFR_IO_ADDR(PINA)
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#else
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#define GCN64_DATA_PORT _SFR_IO_ADDR(PORTD)
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#define GCN64_DATA_DDR _SFR_IO_ADDR(DDRD)
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#define GCN64_DATA_PIN _SFR_IO_ADDR(PIND)
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#endif
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#define GCN64_DATA_BIT 0
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#if F_CPU != 16000000L
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#error Only 16MHz clock supported
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#endif
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/************************************************
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* Function gcn64_receiveBits
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*
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* Works by timing the low and high periods of each bit and
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* then comparing them to know if a 1 or a 0 was on the wire.
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*
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* Example timed values:
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* 54 4e 53 4d 53 4d 53 4e 53 4d 4d 53 53 4e 4c 54 53 4d 54 4d 53 4d 53 4d ...
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* 0 0 0 0 0 1 0 1 0 0 0 0 ....
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*/
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; The bit timeout is a counter to 127. This is the
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; start value. Counting from 0 takes hundreads of
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; microseconds. Because of this, the reception function
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; "hangs in there" much longer than necessary..
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#define TIMING_OFFSET 75
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; unsigned int gcn64_receiveBytes(unsigned char *dstbuf, unsigned char max_bytes);
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; r24,r25 : dstbuf
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; r22 : max bytes (for fututre use)
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; return: count in r24,r25 (0xff: Error, 0xfe: Overflow [max_bytes too low])
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gcn64_receiveBytes:
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clr xl
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clr xh
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mov zl, r24
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mov zh, r25
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clr r18
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ldi r20, 1
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clr r24
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initial_wait_low:
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inc r18
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breq timeout ; overflow to 0
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sbic GCN64_DATA_PIN, GCN64_DATA_BIT
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rjmp initial_wait_low
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; the next transition is to a high bit
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rjmp waithigh
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waitlow:
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mov r21, r18 ; Save the last value
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ldi r18, TIMING_OFFSET
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waitlow_lp:
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inc r18
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brmi rxdone ; > 127 (approx 50uS timeout)
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sbic GCN64_DATA_PIN, GCN64_DATA_BIT
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rjmp waitlow_lp
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; Compare the low period and the high period.
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sub r19, r18 ; Carry is set when 1
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rol r20
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brcs store_byte
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rjmp waithigh
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store_byte:
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cp r22, r24 ; Check max_bytes
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breq overflow
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inc r24 ; Count byte
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st z+,r20
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ldi r20, 1
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waithigh:
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ldi r19, TIMING_OFFSET
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waithigh_lp:
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inc r19
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brmi frame_error ; This means the line is stuck in a low state...
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sbis GCN64_DATA_PIN, GCN64_DATA_BIT
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rjmp waithigh_lp
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rjmp waitlow
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overflow:
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ser r24 ; 0xff
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dec r24 ; 0xfe
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ret
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timeout:
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tst r24
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breq rxdone ; If r24 is still zero, we did not receive anything. Return 0.
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; Otherwise, it is a frame error (i.e. A partial byte was received)
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frame_error:
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ser r24
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rxdone:
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; Return the number if received bits in r24
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ret
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; These are for a slower 4us/1.5us timing.
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; The MadCatz Microcon does not work with 3us/1us timing...
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#define LOOPS_SEND0_LOW 20
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#define DELAY_SEND0_HIGH 2
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#define LOOPS_SEND1_LOW 4
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#define LOOPS_SEND1_HIGH 13
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/*
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; These are for the perfect 3us/1us timing described below
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#define LOOPS_SEND0_LOW 15
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#define LOOPS_SEND1_LOW 4
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#define LOOPS_SEND1_HIGH 10
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*/
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/************************************************
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* Send data using the N64/GC serial protocol which
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* is as follows:
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* 0 1
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* __ _____
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* ____| __|
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* ^ ^ ^ ^ ^ ^
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* 3us 1us 1us 3us
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*
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* To send a 1, the pin direction is set to input.
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* To send a 0, the pin direction is set to output.
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* (of course, it's value is preset to zero)
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*
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* At 16 mhz, a 1us period is 16 cycles. Thus a 3us period
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* is 48 cycles.
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*
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* Pointer to data is passed in r24, r25
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* Number of bytes to send is passed in r22
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*
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* A stop bit is added at thy end of the packet.
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*
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************************************************/
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gcn64_sendBytes:
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; Move r23,r24 pointer to z
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mov zl, r24
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mov zh, r25
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tst r22
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breq done_send
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send_next_byte:
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; Check if this is the last byte.
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tst r22
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breq send_stop
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dec r22
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ld r21, z+
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ldi r27, 0x80 ; mask
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send_next_bit:
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mov r19, r21
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and r19, r27
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brne send1
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nop
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send0:
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sbi GCN64_DATA_DDR, GCN64_DATA_BIT ; Pull bus to 0
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ldi r20, LOOPS_SEND0_LOW
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lp_send0_3us:
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dec r20
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brne lp_send0_3us
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nop
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cbi GCN64_DATA_DDR, GCN64_DATA_BIT ; Release bus to 1
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#ifdef DELAY_SEND0_HIGH
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ldi r20, DELAY_SEND0_HIGH
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lp_send0_1us:
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dec r20
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brne lp_send0_1us
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#endif
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lsr r27
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breq send_next_byte
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nop
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nop
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nop
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nop
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nop
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nop
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rjmp send_next_bit
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send1:
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sbi GCN64_DATA_DDR, GCN64_DATA_BIT ; Pull bus to 0
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ldi r20, LOOPS_SEND1_LOW
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lp_send1_1us:
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dec r20
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brne lp_send1_1us
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nop
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nop
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cbi GCN64_DATA_DDR, GCN64_DATA_BIT ; Release bus to 1
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ldi r20, LOOPS_SEND1_HIGH
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lp_send1_3us:
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dec r20
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brne lp_send1_3us
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nop
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nop
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lsr r27
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breq send_next_byte
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nop
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nop
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nop
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nop
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nop
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nop
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rjmp send_next_bit
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send_stop:
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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; STOP BIT
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sbi GCN64_DATA_DDR, GCN64_DATA_BIT ; Pull low for stop bit
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ldi r20, LOOPS_SEND1_LOW
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stbdly0:
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dec r20
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brne stbdly0
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nop
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cbi GCN64_DATA_DDR, GCN64_DATA_BIT ; Release
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done_send:
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ret
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