mirror of
https://github.com/raphnet/gc_n64_usb-v3
synced 2025-02-07 02:30:14 -05:00
Half the memory footprint for reception code
This commit is contained in:
Raphael Assenat
parent
cb9be3f604
commit
6aaccb0eb3
@ -71,54 +71,6 @@ void gcn64_protocol_getBytes(int offset, int n_bytes, unsigned char *dstbuf)
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}
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}
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/* \brief Decode the received length of low/high states to byte-per-bit format
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*
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* The result is in workbuf.
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*
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**/
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static void gcn64_decodeWorkbuf(unsigned int count)
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{
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unsigned int i;
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volatile unsigned char *output = gcn64_workbuf;
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volatile unsigned char *input = gcn64_workbuf;
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unsigned char t;
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//
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// ________
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// ________/
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//
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// [i*2] [i*2+1]
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//
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// ________________
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// 0 : ____/
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// ____
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// 1 : ________________/
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//
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// The timings on a real N64 are
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//
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// 0 : 1 us low, 3 us high
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// 1 : 3 us low, 1 us high
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//
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// However, HORI pads use something similar to
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//
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// 0 : 1.5 us low, 4.5 us high
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// 1 : 4.5 us low, 1.5 us high
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//
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//
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// No64 us = microseconds
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// This operation takes approximately 100uS on 64bit gamecube messages
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for (i=0; i<count; i++) {
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t = *input;
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input++;
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*output = t < *input;
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input++;
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output++;
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}
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}
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void gcn64protocol_hwinit(void)
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{
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// data as input
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@ -133,8 +85,6 @@ void gcn64protocol_hwinit(void)
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PORTB &= ~0x10;
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}
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/**
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* \brief Send n data bytes + stop bit, wait for answer.
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* \return The number of bits received, 0 on timeout/error.
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@ -146,15 +96,21 @@ int gcn64_transaction(unsigned char *data_out, int data_out_len)
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{
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int count;
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unsigned char sreg = SREG;
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int i;
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#ifdef DISABLE_INTS_DURING_COMM
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cli();
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#endif
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gcn64_sendBytes(data_out, data_out_len);
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//count = gcn64_receive();
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count = gcn64_receiveBits(gcn64_workbuf, 0);
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SREG = sreg;
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#if 0
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printf("Count: %d { ", count);
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for (i=0; i<count; i++) {
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printf("%02x ", gcn64_workbuf[i]);
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}
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printf("}\r\n");
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#endif
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if (!count)
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return 0;
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@ -168,15 +124,13 @@ int gcn64_transaction(unsigned char *data_out, int data_out_len)
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return 0;
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}
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gcn64_decodeWorkbuf(count);
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/* this delay is required on N64 controllers. Otherwise, after sending
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* a rumble-on or rumble-off command (probably init too), the following
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* get status fails. This starts to work at 2us. 5 should be safe. */
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_delay_us(5);
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* get status fails. This starts to work at 30us. 60us should be safe. */
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_delay_us(60); // Note that this results in a 100us delay between packets.
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/* return the number of full bits received. */
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return (count-1) / 2;
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/* return the number of full bits received, minus the stop bit */
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return count-1;
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}
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61
gcn64txrx.S
61
gcn64txrx.S
@ -10,6 +10,7 @@
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#define yh r29
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#define zl r30
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#define zh r31
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#define __zero_reg__ r1
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/* the value of the gpio is pre-configured to low. We simulate
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an open drain output by toggling the direction */
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@ -29,12 +30,22 @@
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#error Only 16MHz clock supported
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#endif
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/************************************************
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* Function gcn64_receiveBits
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*
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* Works by timing the low and high periods of each bit and
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* then comparing them to know if a 1 or a 0 was on the wire.
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*
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* Example timed values:
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* 54 4e 53 4d 53 4d 53 4e 53 4d 4d 53 53 4e 4c 54 53 4d 54 4d 53 4d 53 4d ...
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* 0 0 0 0 0 1 0 1 0 0 0 0 ....
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*/
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; The bit timeout is a counter to 127. This is the
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; start value. Counting from 0 takes hundreads of
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; microseconds. Because of this, the reception function
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; "hangs in there" much longer than necessary..
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#define TIMING_OFFSET 75
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; unsigned int gcn64_receiveBytes(unsigned char *dstbuf, unsigned char max_bytes);
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; r24,r25 : dstbuf
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; r22 : max bytes (for fututre use)
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@ -44,8 +55,9 @@ gcn64_receiveBits:
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clr xh
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mov zl, r24
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mov zh, r25
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clr r18
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clr r20
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inc r20
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initial_wait_low:
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inc r18
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breq timeout ; overflow to 0
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@ -56,33 +68,60 @@ initial_wait_low:
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rjmp waithigh
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waitlow:
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mov r21, r18 ; Save the last value
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ldi r18, TIMING_OFFSET
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waitlow_lp:
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inc r18
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brmi timeout ; > 127 (approx 50uS timeout)
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brmi timeout_waitlow ; > 127 (approx 50uS timeout)
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sbic GCN64_DATA_PIN, GCN64_DATA_BIT
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rjmp waitlow_lp
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adiw xl, 1 ; count this timed low level
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adiw xl, 1 ; count this bit
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breq overflow ; > 255
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#if 0
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st z+, r19
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st z+, r18
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rjmp waithigh
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#else
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; Compare the low period and the high period.
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sub r19, r18
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brcs got1
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got0:
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st z+, __zero_reg__
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rjmp waithigh
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got1:
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st z+,r20
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#endif
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waithigh:
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ldi r18, TIMING_OFFSET
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ldi r19, TIMING_OFFSET
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waithigh_lp:
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inc r18
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inc r19
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brmi timeout ; > 127
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sbis GCN64_DATA_PIN, GCN64_DATA_BIT
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rjmp waithigh_lp
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adiw xl, 1 ; count this timed high level
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breq overflow ; > 255
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st z+,r18
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rjmp waitlow
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timeout_waitlow:
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adiw xl, 1 ;
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breq overflow ; > 255
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; Compare the low period and the high period.
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sub r19, r21
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brcs lastwas1
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lastwas0:
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st z+, __zero_reg__
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rjmp rxdone
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lastwas1:
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st z+,r20
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rjmp rxdone
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overflow:
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clr xl
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clr xh
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timeout:
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rxdone:
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; Return the number if received bits in r24,r25
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mov r24, xl ; yl
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mov r25, xh ; yh
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