mirror of
https://github.com/raphnet/dreamcast_usb
synced 2024-11-18 07:04:59 -05:00
435 lines
8.3 KiB
C
435 lines
8.3 KiB
C
/* Dreamcast to USB : Sega dc controllers to USB adapter
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* Copyright (C) 2013 Raphaël Assénat
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The author may be contacted at raph@raphnet.net
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*/
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#include <avr/io.h>
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#include <util/delay.h>
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#include <string.h>
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#include "maplebus.h"
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#undef NOLRC
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#undef TRACE_RX_START_END
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#undef TRACE_DECODED
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#undef TRACE_PIN1_BITS
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//
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//
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// PORTC0 : Pin 1
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// PORTC1 : Pin 5
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//
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void maple_init(void)
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{
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DDRC = 0xFC;
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PORTC = 0x03;
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}
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#define transmitMode() do { PORTC |= 0x03; DDRC |= 0x03; } while(0)
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#define inputMode() do { PORTC |= 0x03; DDRC &= ~0x03; } while(0)
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#define MAPLE_BUF_SIZE 641
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static unsigned char maplebuf[MAPLE_BUF_SIZE];
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static unsigned char buf_used;
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static unsigned char buf_phase;
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#define PIN_1 0x01
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#define PIN_5 0x02
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static void buf_reset(void)
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{
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buf_used = 0;
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buf_phase = 0;
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}
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static void buf_addBit(char value)
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{
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// The values in maplebuf will be written
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// directly to PORTC. Unused bits will be low.
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if (buf_phase & 0x01) {
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maplebuf[buf_used] = PIN_5;
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if (value) {
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maplebuf[buf_used] |= PIN_1; // prepare data
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}
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buf_used++;
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}
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else {
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maplebuf[buf_used] = PIN_1;
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if (value) {
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maplebuf[buf_used] |= PIN_5; // prepare data
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}
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buf_used++;
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}
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buf_phase ^= 1;
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}
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static int maplebus_decode(unsigned char *data, unsigned int maxlen)
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{
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unsigned char dst_b;
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unsigned int dst_pos;
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unsigned char last;
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unsigned char last_fell;
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int i;
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#ifdef TRACE_DECODED
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PORTB |= 0x10;
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PORTB &= ~0x10;
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PORTB |= 0x10;
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PORTB &= ~0x10;
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PORTB |= 0x10;
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PORTB &= ~0x10;
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#endif
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// Look for the initial phase 1 (Pin 1 high, Pin 5 low). This
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// is to skip what we got of the sync/start of frame sequence.
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//
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for (i=0; i<MAPLE_BUF_SIZE; i++) {
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if ((maplebuf[i]&0x03) == 0x01)
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break;
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}
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if (i==MAPLE_BUF_SIZE) {
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return -1; // timeout
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}
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dst_pos = 0;
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data[0] = 0;
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dst_b = 0x80;
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last = maplebuf[i] & 0x03;
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last_fell = 0;
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for (; i<MAPLE_BUF_SIZE; i++) {
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unsigned char fell;
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unsigned char cur = maplebuf[i] & 0x3;
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#ifdef TRACE_PIN1_BITS
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if (cur & 1) {
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PORTB |= 0x10;
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} else {
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PORTB &= ~0x10;
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}
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#endif
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if (cur == last) {
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continue; // no change
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}
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fell = last & (cur ^ last);
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if (!fell) {
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// pin(s) changed, but none fell.
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last = cur;
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continue;
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}
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if (fell == last_fell) {
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// two identical consecutive phases marks the end of the packet.
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#ifdef TRACE_DECODED
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PORTB |= 0x10;
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PORTB &= ~0x10;
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PORTB |= 0x10;
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PORTB &= ~0x10;
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PORTB |= 0x10;
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PORTB &= ~0x10;
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#endif
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break;
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}
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// when any of the two pins fall, the
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// other pin is the data.
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if (fell) {
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if (fell == 0x03) {
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// two pins at the same time!
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PORTB |= 0x10;
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PORTB &= ~0x10;
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}
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if (cur) {
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data[dst_pos] |= dst_b;
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#ifdef TRACE_DECODED
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PORTB |= 0x10;
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#endif
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}
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else {
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#ifdef TRACE_DECODED
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PORTB &= ~0x10;
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#endif
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}
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}
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dst_b >>= 1;
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if (!dst_b) {
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dst_b = 0x80;
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dst_pos++;
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if (dst_pos >= maxlen) {
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#ifdef TRACE_DECODED
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PORTB &= ~0x10;
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#endif
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return -3;
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}
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data[dst_pos] = 0;
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}
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last_fell = fell;
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last = cur;
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}
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#ifdef TRACE_DECODED
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PORTB &= ~0x10;
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#endif
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return dst_pos;
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}
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/**
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* \param data Destination buffer to store reply (payload + crc + eot)
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* \param maxlen The length of the destination buffer
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* \return -1 on timeout, -2 lrc/frame error, -3 too much data. Otherwise the number of bytes received
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*/
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int maple_receiveFrame(unsigned char *data, unsigned int maxlen)
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{
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unsigned char *tmp = maplebuf;
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unsigned char lrc;
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unsigned char timeout;
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int res, i;
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//
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// __ _ _ _
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// |_____| |_| |_| |_
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// ___ _ _ _
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// |_| |___| |_| |_
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// 310022011023102310
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// ^ ^ ^ ^^ ^^
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//
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asm volatile(
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" push r30 \n" // 2
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" push r31 \n" // 2
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" clr %1 \n" // 1 (result=0, no timeout)
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// " sbi 0x5, 4 \n" // PB4
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// " cbi 0x5, 4 \n"
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// Loop until a change is detected.
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" ldi r18, 255 \n"
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" in r17, %2 \n"
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"wait_start: \n"
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" dec r18 \n"
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" breq timeout \n"
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" in r16, %2 \n"
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" cp r16, r17 \n"
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" breq wait_start \n"
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" rjmp start_rx \n"
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"timeout:\n"
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" inc %1 \n" // 1 for timeout
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" sbi 0x5, 4 \n" // PB4
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" cbi 0x5, 4 \n"
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" jmp done \n"
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"start_rx: \n"
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#ifdef TRACE_RX_START_END
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" sbi 0x5, 4 \n" // PB4
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" cbi 0x5, 4 \n"
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#endif
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// We will loose the first bit(s), but
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// it's only the start of frame.
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#include "rxcode.asm"
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"done:\n"
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#ifdef TRACE_RX_START_END
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" sbi 0x5, 4 \n" // PB4
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" cbi 0x5, 4 \n"
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#endif
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" pop r31 \n" // 2
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" pop r30 \n" // 2
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: "=z"(tmp), "=r"(timeout)
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: "I" (_SFR_IO_ADDR(PINC))
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: "r16","r17","r18") ;
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if (timeout)
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return -1;
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res = maplebus_decode(data, maxlen);
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if (res<=0)
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return res;
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// A packet contains n groups of 4 bytes, plus 1 byte crc.
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if (((res-1) & 0x3) != 0) {
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return -2; // frame error
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}
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#ifndef NOLRC
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for (lrc=0, i=0; i<res; i++) {
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lrc ^= data[i];
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}
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if (lrc)
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return -2; // LRC error
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#endif
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/* Reverse each group of 4 bytes */
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for (i=0; i<(res-1); i+=4) {
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unsigned char tmp;
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tmp = data[i+3];
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data[i+3] = data[i];
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data[i] = tmp;
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tmp = data[i+2];
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data[i+2] = data[i+1];
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data[i+1] = tmp;
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}
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return res-1; // remove lrc
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}
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void maple_sendRaw(unsigned char *data, unsigned char len)
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{
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int i;
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unsigned char b;
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buf_reset();
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for (i=0; i<len; i++) {
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for (b=0x80; b; b>>=1)
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{
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buf_addBit(data[i] & b);
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}
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}
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// Output
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transmitMode();
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// DC controller pin 1 and pin 5
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#define SET_1 " sbi %0, 0\n"
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#define CLR_1 " cbi %0, 0\n"
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#define SET_5 " sbi %0, 1\n"
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#define CLR_5 " cbi %0, 1\n"
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#define DLY_8 " nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\n"
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#define DLY_5 " nop\nnop\nnop\nnop\nnop\n"
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#define DLY_4 " nop\nnop\nnop\nnop\n"
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#define DLY_3 " nop\nnop\nnop\n"
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asm volatile(
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"push r31\n"
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"push r30\n"
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"mov r19, %1 \n" // Length in bytes
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"ldi r20, 0x01 \n" // phase 1 pin 1 high, pin 5 low
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"ldi r21, 0x02 \n" // phase 2 pin 1 low, pin 2 high
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"ld r16, z+ \n"
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// Sync
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SET_1 SET_5 DLY_8
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CLR_1 DLY_4
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CLR_5 DLY_3
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SET_5 DLY_3
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CLR_5
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DLY_3
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SET_5
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DLY_3
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CLR_5
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DLY_3
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SET_5
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DLY_3
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CLR_5 DLY_3 SET_5
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DLY_5 SET_1 CLR_5
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// Pin 5 is low, Pin 1 is high. Ready for 1st phase
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// Note: Coded for 16Mhz (8 cycles = 500ns)
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"next_byte:\n"
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"out %0, r20 \n" // 1 initial phase 1 state
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// "nop \n" // 1
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"out %0, r16 \n" // 1 data
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"cbi %0, 0 \n" // 1 falling edge on pin 1
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"ld r16, z+ \n" // 2 load phase 2 data
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// "nop \n" // 1
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"out %0, r21 \n" // 1 initial phase 2 state
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// "nop \n"
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"out %0, r16 \n" // 1 data
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"cbi %0, 1 \n" // 1 falling edge on pin 5
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"ld r16, z+ \n" // 2
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"dec r19 \n" // 1 Decrement counter for brne below
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"brne next_byte \n" // 2
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// End of transmission
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SET_1
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DLY_4
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SET_5 CLR_5 DLY_3
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CLR_1
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DLY_3
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SET_1
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DLY_3
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CLR_1
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DLY_3
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SET_1
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DLY_3
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SET_5
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"pop r30 \n"
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"pop r31 \n"
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:
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: "I" (_SFR_IO_ADDR(PORTC)), "r"(buf_used/2), "z"(maplebuf)
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: "r1","r16","r17","r18","r19","r20","r21"
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);
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// back to input to receive the answer
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inputMode();
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}
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void maple_sendFrame1W(uint8_t cmd, uint8_t dst_addr, uint8_t src_addr, uint32_t data)
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{
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uint8_t tmp[4] = { data, data >> 8, data >> 16, data >> 24 };
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maple_sendFrame(cmd, dst_addr, src_addr, 4, tmp);
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}
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/*
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* data is in bus order
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*/
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void maple_sendFrame(uint8_t cmd, uint8_t dst_addr, uint8_t src_addr, int data_len, uint8_t *data)
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{
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uint8_t tmp[4 + data_len + 1]; // header, data and LRC
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//uint8_t *d;
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uint8_t lrc=0;
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int i;
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tmp[0] = data_len >> 2;
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tmp[1] = src_addr;
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tmp[2] = dst_addr;
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tmp[3] = cmd;
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if (data_len) {
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memcpy(tmp + 4, data, data_len);
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}
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for (lrc=0, i=0; i<data_len+4; i++) {
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lrc ^= tmp[i];
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}
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tmp[i] = lrc;
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maple_sendRaw(tmp, sizeof(tmp));
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}
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