mirror of
https://github.com/raphnet/dreamcast_usb
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393 lines
15 KiB
PHP
393 lines
15 KiB
PHP
/* Name: usbdrvasm12.inc
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* Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
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* Author: Christian Starkjohann
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* Creation Date: 2004-12-29
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* Tabsize: 4
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* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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* License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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*/
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/* Do not link this file! Link usbdrvasm.S instead, which includes the
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* appropriate implementation!
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*/
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/*
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General Description:
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This file is the 12 MHz version of the asssembler part of the USB driver. It
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requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
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oscillator).
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See usbdrv.h for a description of the entire driver.
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Since almost all of this code is timing critical, don't change unless you
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really know what you are doing! Many parts require not only a maximum number
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of CPU cycles, but even an exact number of cycles!
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Timing constraints according to spec (in bit times):
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timing subject min max CPUcycles
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---------------------------------------------------------------------------
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EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
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EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
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DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
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*/
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;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
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;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
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;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
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;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
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;Numbers in brackets are maximum cycles since SOF.
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USB_INTR_VECTOR:
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;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
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push YL ;2 [35] push only what is necessary to sync with edge ASAP
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in YL, SREG ;1 [37]
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push YL ;2 [39]
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;----------------------------------------------------------------------------
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; Synchronize with sync pattern:
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;----------------------------------------------------------------------------
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;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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;sync up with J to K edge during sync pattern -- use fastest possible loops
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;The first part waits at most 1 bit long since we must be in sync pattern.
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;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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;waitForJ, ensure that this prerequisite is met.
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waitForJ:
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inc YL
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sbis USBIN, USBMINUS
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brne waitForJ ; just make sure we have ANY timeout
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waitForK:
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;The following code results in a sampling window of 1/4 bit which meets the spec.
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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#if USB_COUNT_SOF
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lds YL, usbSofCount
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inc YL
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sts usbSofCount, YL
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#endif /* USB_COUNT_SOF */
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#ifdef USB_SOF_HOOK
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USB_SOF_HOOK
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#endif
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rjmp sofError
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foundK:
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;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
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;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
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;are cycles from center of first sync (double K) bit after the instruction
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push YH ;2 [2]
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lds YL, usbInputBufOffset;2 [4]
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clr YH ;1 [5]
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subi YL, lo8(-(usbRxBuf));1 [6]
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sbci YH, hi8(-(usbRxBuf));1 [7]
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sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
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rjmp haveTwoBitsK ;2 [10]
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pop YH ;2 [11] undo the push from before
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rjmp waitForK ;2 [13] this was not the end of sync, retry
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haveTwoBitsK:
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;----------------------------------------------------------------------------
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; push more registers and initialize values while we sample the first bits:
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;----------------------------------------------------------------------------
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push shift ;2 [16]
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push x1 ;2 [12]
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push x2 ;2 [14]
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in x1, USBIN ;1 [17] <-- sample bit 0
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ldi shift, 0xff ;1 [18]
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bst x1, USBMINUS ;1 [19]
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bld shift, 0 ;1 [20]
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push x3 ;2 [22]
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push cnt ;2 [24]
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in x2, USBIN ;1 [25] <-- sample bit 1
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ser x3 ;1 [26] [inserted init instruction]
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eor x1, x2 ;1 [27]
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bst x1, USBMINUS ;1 [28]
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bld shift, 1 ;1 [29]
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ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
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rjmp rxbit2 ;2 [32]
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;----------------------------------------------------------------------------
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; Receiver loop (numbers in brackets are cycles within byte after instr)
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;----------------------------------------------------------------------------
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unstuff0: ;1 (branch taken)
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andi x3, ~0x01 ;1 [15]
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mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
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in x2, USBIN ;1 [17] <-- sample bit 1 again
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ori shift, 0x01 ;1 [18]
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rjmp didUnstuff0 ;2 [20]
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unstuff1: ;1 (branch taken)
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mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
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andi x3, ~0x02 ;1 [22]
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ori shift, 0x02 ;1 [23]
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nop ;1 [24]
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in x1, USBIN ;1 [25] <-- sample bit 2 again
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rjmp didUnstuff1 ;2 [27]
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unstuff2: ;1 (branch taken)
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andi x3, ~0x04 ;1 [29]
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ori shift, 0x04 ;1 [30]
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mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
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nop ;1 [32]
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in x2, USBIN ;1 [33] <-- sample bit 3
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rjmp didUnstuff2 ;2 [35]
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unstuff3: ;1 (branch taken)
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in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
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andi x3, ~0x08 ;1 [35]
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ori shift, 0x08 ;1 [36]
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rjmp didUnstuff3 ;2 [38]
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unstuff4: ;1 (branch taken)
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andi x3, ~0x10 ;1 [40]
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in x1, USBIN ;1 [41] <-- sample stuffed bit 4
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ori shift, 0x10 ;1 [42]
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rjmp didUnstuff4 ;2 [44]
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unstuff5: ;1 (branch taken)
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andi x3, ~0x20 ;1 [48]
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in x2, USBIN ;1 [49] <-- sample stuffed bit 5
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ori shift, 0x20 ;1 [50]
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rjmp didUnstuff5 ;2 [52]
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unstuff6: ;1 (branch taken)
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andi x3, ~0x40 ;1 [56]
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in x1, USBIN ;1 [57] <-- sample stuffed bit 6
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ori shift, 0x40 ;1 [58]
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rjmp didUnstuff6 ;2 [60]
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; extra jobs done during bit interval:
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; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
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; bit 1: se0 check
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; bit 2: overflow check
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; bit 3: recovery from delay [bit 0 tasks took too long]
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; bit 4: none
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; bit 5: none
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; bit 6: none
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; bit 7: jump, eor
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rxLoop:
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eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
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in x1, USBIN ;1 [1] <-- sample bit 0
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st y+, x3 ;2 [3] store data
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ser x3 ;1 [4]
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nop ;1 [5]
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eor x2, x1 ;1 [6]
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bst x2, USBMINUS;1 [7]
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bld shift, 0 ;1 [8]
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in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
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andi x2, USBMASK ;1 [10]
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breq se0 ;1 [11] SE0 check for bit 1
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andi shift, 0xf9 ;1 [12]
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didUnstuff0:
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breq unstuff0 ;1 [13]
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eor x1, x2 ;1 [14]
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bst x1, USBMINUS;1 [15]
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bld shift, 1 ;1 [16]
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rxbit2:
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in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
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andi shift, 0xf3 ;1 [18]
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breq unstuff1 ;1 [19] do remaining work for bit 1
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didUnstuff1:
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subi cnt, 1 ;1 [20]
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brcs overflow ;1 [21] loop control
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eor x2, x1 ;1 [22]
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bst x2, USBMINUS;1 [23]
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bld shift, 2 ;1 [24]
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in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
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andi shift, 0xe7 ;1 [26]
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breq unstuff2 ;1 [27]
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didUnstuff2:
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eor x1, x2 ;1 [28]
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bst x1, USBMINUS;1 [29]
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bld shift, 3 ;1 [30]
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didUnstuff3:
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andi shift, 0xcf ;1 [31]
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breq unstuff3 ;1 [32]
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in x1, USBIN ;1 [33] <-- sample bit 4
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eor x2, x1 ;1 [34]
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bst x2, USBMINUS;1 [35]
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bld shift, 4 ;1 [36]
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didUnstuff4:
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andi shift, 0x9f ;1 [37]
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breq unstuff4 ;1 [38]
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nop2 ;2 [40]
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in x2, USBIN ;1 [41] <-- sample bit 5
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eor x1, x2 ;1 [42]
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bst x1, USBMINUS;1 [43]
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bld shift, 5 ;1 [44]
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didUnstuff5:
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andi shift, 0x3f ;1 [45]
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breq unstuff5 ;1 [46]
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nop2 ;2 [48]
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in x1, USBIN ;1 [49] <-- sample bit 6
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eor x2, x1 ;1 [50]
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bst x2, USBMINUS;1 [51]
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bld shift, 6 ;1 [52]
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didUnstuff6:
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cpi shift, 0x02 ;1 [53]
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brlo unstuff6 ;1 [54]
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nop2 ;2 [56]
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in x2, USBIN ;1 [57] <-- sample bit 7
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eor x1, x2 ;1 [58]
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bst x1, USBMINUS;1 [59]
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bld shift, 7 ;1 [60]
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didUnstuff7:
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cpi shift, 0x04 ;1 [61]
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brsh rxLoop ;2 [63] loop control
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unstuff7:
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andi x3, ~0x80 ;1 [63]
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ori shift, 0x80 ;1 [64]
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in x2, USBIN ;1 [65] <-- sample stuffed bit 7
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nop ;1 [66]
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rjmp didUnstuff7 ;2 [68]
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macro POP_STANDARD ; 12 cycles
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pop cnt
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pop x3
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pop x2
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pop x1
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pop shift
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pop YH
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endm
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macro POP_RETI ; 5 cycles
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pop YL
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out SREG, YL
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pop YL
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endm
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#include "asmcommon.inc"
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;----------------------------------------------------------------------------
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; Transmitting data
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;----------------------------------------------------------------------------
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txByteLoop:
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txBitloop:
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stuffN1Delay: ; [03]
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ror shift ;[-5] [11] [59]
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brcc doExorN1 ;[-4] [60]
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subi x4, 1 ;[-3]
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brne commonN1 ;[-2]
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lsl shift ;[-1] compensate ror after rjmp stuffDelay
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nop ;[00] stuffing consists of just waiting 8 cycles
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rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear
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sendNakAndReti: ;0 [-19] 19 cycles until SOP
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ldi x3, USBPID_NAK ;1 [-18]
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rjmp usbSendX3 ;2 [-16]
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sendAckAndReti: ;0 [-19] 19 cycles until SOP
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ldi x3, USBPID_ACK ;1 [-18]
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rjmp usbSendX3 ;2 [-16]
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sendCntAndReti: ;0 [-17] 17 cycles until SOP
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mov x3, cnt ;1 [-16]
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usbSendX3: ;0 [-16]
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ldi YL, 20 ;1 [-15] 'x3' is R20
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ldi YH, 0 ;1 [-14]
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ldi cnt, 2 ;1 [-13]
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; rjmp usbSendAndReti fallthrough
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; USB spec says:
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; idle = J
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; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
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; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
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; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
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;usbSend:
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;pointer to data in 'Y'
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;number of bytes in 'cnt' -- including sync byte
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;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt]
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;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction)
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usbSendAndReti:
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in x2, USBDDR ;[-12] 12 cycles until SOP
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ori x2, USBMASK ;[-11]
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sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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out USBDDR, x2 ;[-8] <--- acquire bus
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in x1, USBOUT ;[-7] port mirror for tx loop
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ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror)
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ldi x2, USBMASK ;[-5]
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push x4 ;[-4]
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doExorN1:
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eor x1, x2 ;[-2] [06] [62]
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ldi x4, 6 ;[-1] [07] [63]
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commonN1:
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stuffN2Delay:
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out USBOUT, x1 ;[00] [08] [64] <--- set bit
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ror shift ;[01]
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brcc doExorN2 ;[02]
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subi x4, 1 ;[03]
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brne commonN2 ;[04]
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lsl shift ;[05] compensate ror after rjmp stuffDelay
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rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear
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doExorN2:
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eor x1, x2 ;[04] [12]
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ldi x4, 6 ;[05] [13]
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commonN2:
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nop ;[06] [14]
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subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1
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out USBOUT, x1 ;[08] [16] <--- set bit
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brcs txBitloop ;[09] [25] [41]
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stuff6Delay:
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ror shift ;[42] [50]
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brcc doExor6 ;[43]
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subi x4, 1 ;[44]
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brne common6 ;[45]
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lsl shift ;[46] compensate ror after rjmp stuffDelay
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nop ;[47] stuffing consists of just waiting 8 cycles
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rjmp stuff6Delay ;[48] after ror, C bit is reliably clear
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doExor6:
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eor x1, x2 ;[45] [53]
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ldi x4, 6 ;[46]
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common6:
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stuff7Delay:
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ror shift ;[47] [55]
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out USBOUT, x1 ;[48] <--- set bit
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brcc doExor7 ;[49]
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subi x4, 1 ;[50]
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brne common7 ;[51]
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lsl shift ;[52] compensate ror after rjmp stuffDelay
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rjmp stuff7Delay ;[53] after ror, C bit is reliably clear
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doExor7:
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eor x1, x2 ;[51] [59]
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ldi x4, 6 ;[52]
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common7:
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ld shift, y+ ;[53]
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tst cnt ;[55]
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out USBOUT, x1 ;[56] <--- set bit
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brne txByteLoop ;[57]
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;make SE0:
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cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles]
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lds x2, usbNewDeviceAddr;[59]
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lsl x2 ;[61] we compare with left shifted address
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subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3
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sbci YH, 0 ;[63]
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out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
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;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
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;set address only after data packet was sent, not after handshake
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breq skipAddrAssign ;[01]
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sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
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skipAddrAssign:
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;end of usbDeviceAddress transfer
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ldi x2, 1<<USB_INTR_PENDING_BIT;[03] int0 occurred during TX -- clear pending flag
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USB_STORE_PENDING(x2) ;[04]
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ori x1, USBIDLE ;[05]
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in x2, USBDDR ;[06]
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cbr x2, USBMASK ;[07] set both pins to input
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mov x3, x1 ;[08]
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cbr x3, USBMASK ;[09] configure no pullup on both pins
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pop x4 ;[10]
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nop2 ;[12]
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nop2 ;[14]
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out USBOUT, x1 ;[16] <-- out J (idle) -- end of SE0 (EOP signal)
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out USBDDR, x2 ;[17] <-- release bus now
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out USBOUT, x3 ;[18] <-- ensure no pull-up resistors are active
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rjmp doReturn
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