52 lines
1.8 KiB
C
52 lines
1.8 KiB
C
#ifndef ULTRA64_RDP_H
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#define ULTRA64_RDP_H
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/* DP Command Registers */
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#define DPC_REG_BASE 0xA4100000
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#define DPC_START_REG (*(vu32*)(DPC_REG_BASE + 0x00))
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#define DPC_END_REG (*(vu32*)(DPC_REG_BASE + 0x04))
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#define DPC_CURRENT_REG (*(vu32*)(DPC_REG_BASE + 0x08))
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#define DPC_STATUS_REG (*(vu32*)(DPC_REG_BASE + 0x0C))
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#define DPC_CLOCK_REG (*(vu32*)(DPC_REG_BASE + 0x10))
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#define DPC_BUFBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x14))
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#define DPC_PIPEBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x18))
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#define DPC_TMEM_REG (*(vu32*)(DPC_REG_BASE + 0x1C))
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/* DP Span Registers */
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#define DPS_REG_BASE 0xA4200000
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#define DPS_TBIST_REG (*(vu32*)(DPS_REG_BASE + 0x00))
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#define DPS_TEST_MODE_REG (*(vu32*)(DPS_REG_BASE + 0x04))
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#define DPS_BUFTEST_ADDR_REG (*(vu32*)(DPS_REG_BASE + 0x08))
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#define DPS_BUFTEST_DATA_REG (*(vu32*)(DPS_REG_BASE + 0x0C))
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/* DP Status Read Flags */
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#define DPC_STATUS_XBUS_DMEM_DMA 0x001
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#define DPC_STATUS_FREEZE 0x002
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#define DPC_STATUS_FLUSH 0x004
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#define DPC_STATUS_START_GCLK 0x008
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#define DPC_STATUS_TMEM_BUSY 0x010
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#define DPC_STATUS_PIPE_BUSY 0x020
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#define DPC_STATUS_CMD_BUSY 0x040
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#define DPC_STATUS_CBUF_READY 0x080
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#define DPC_STATUS_DMA_BUSY 0x100
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#define DPC_STATUS_END_VALID 0x200
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#define DPC_STATUS_START_VALID 0x400
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/* DP Status Write Flags */
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#define DPC_CLR_XBUS_DMEM_DMA 0x0001
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#define DPC_SET_XBUS_DMEM_DMA 0x0002
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#define DPC_CLR_FREEZE 0x0004
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#define DPC_SET_FREEZE 0x0008
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#define DPC_CLR_FLUSH 0x0010
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#define DPC_SET_FLUSH 0x0020
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#define DPC_CLR_TMEM_CTR 0x0040
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#define DPC_CLR_PIPE_CTR 0x0080
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#define DPC_CLR_CMD_CTR 0x0100
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#define DPC_CLR_CLOCK_CTR 0x0200
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#endif
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