84 lines
2.1 KiB
C
84 lines
2.1 KiB
C
#ifndef ULTRA64_PI_H
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#define ULTRA64_PI_H
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#include "message.h"
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typedef struct {
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/* 0x00 */ u32 errStatus;
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/* 0x04 */ void* dramAddr;
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/* 0x08 */ void* C2Addr;
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/* 0x0C */ u32 sectorSize;
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/* 0x10 */ u32 C1ErrNum;
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/* 0x14 */ u32 C1ErrSector[4];
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} __OSBlockInfo; // size = 0x24
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typedef struct {
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/* 0x00 */ u32 cmdType;
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/* 0x04 */ u16 transferMode;
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/* 0x06 */ u16 blockNum;
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/* 0x08 */ s32 sectorNum;
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/* 0x0C */ u32 devAddr;
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/* 0x10 */ u32 bmCtlShadow;
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/* 0x14 */ u32 seqCtlShadow;
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/* 0x18 */ __OSBlockInfo block[2];
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} __OSTranxInfo; // size = 0x60
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typedef struct OSPiHandle {
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/* 0x00 */ struct OSPiHandle* next;
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/* 0x04 */ u8 type;
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/* 0x05 */ u8 latency;
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/* 0x06 */ u8 pageSize;
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/* 0x07 */ u8 relDuration;
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/* 0x08 */ u8 pulse;
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/* 0x09 */ u8 domain;
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/* 0x0C */ u32 baseAddress;
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/* 0x10 */ u32 speed;
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/* 0x14 */ __OSTranxInfo transferInfo;
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} OSPiHandle; // size = 0x74
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typedef struct {
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/* 0x00 */ u8 type;
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/* 0x04 */ u32 address;
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} OSPiInfo; // size = 0x08
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typedef struct {
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/* 0x00 */ u16 type;
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/* 0x02 */ u8 pri;
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/* 0x03 */ u8 status;
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/* 0x04 */ OSMesgQueue* retQueue;
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} OSIoMesgHdr; // size = 0x08
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typedef struct {
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/* 0x00 */ OSIoMesgHdr hdr;
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/* 0x08 */ void* dramAddr;
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/* 0x0C */ u32 devAddr;
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/* 0x10 */ size_t size;
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/* 0x14 */ OSPiHandle* piHandle;
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} OSIoMesg; // size = 0x18
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#define OS_READ 0 // device -> RDRAM
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#define OS_WRITE 1 // device <- RDRAM
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#define OS_OTHERS 2 // for disk drive transfers
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#define PI_DOMAIN1 0
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#define PI_DOMAIN2 1
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#define OS_MESG_TYPE_LOOPBACK 10
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#define OS_MESG_TYPE_DMAREAD 11
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#define OS_MESG_TYPE_DMAWRITE 12
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#define OS_MESG_TYPE_VRETRACE 13
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#define OS_MESG_TYPE_COUNTER 14
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#define OS_MESG_TYPE_EDMAREAD 15
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#define OS_MESG_TYPE_EDMAWRITE 16
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#define OS_MESG_PRI_NORMAL 0
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#define OS_MESG_PRI_HIGH 1
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#define DEVICE_TYPE_CART 0 /* ROM cartridge */
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#define DEVICE_TYPE_BULK 1 /* ROM bulk */
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#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
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#define DEVICE_TYPE_SRAM 3 /* SRAM */
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#define DEVICE_TYPE_INIT 7 /* initial value */
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#endif
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