368 lines
16 KiB
C
368 lines
16 KiB
C
#ifndef ULTRA64_R4300_H
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#define ULTRA64_R4300_H
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#ifdef _LANGUAGE_C
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#include "types.h"
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#define U32(x) ((u32)x)
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#define C_REG(x) (x)
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#else
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#define U32(x) (x)
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#define C_REG(x) $x
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#endif
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// Segment base addresses and sizes
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#define KUBASE 0
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#define KUSIZE 0x80000000
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#define K0BASE 0x80000000
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#define K0SIZE 0x20000000
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#define K1BASE 0xA0000000
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#define K1SIZE 0x20000000
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#define K2BASE 0xC0000000
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#define K2SIZE 0x20000000
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// Exception vectors
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#define SIZE_EXCVEC 0x80 // Size of an exc. vec
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#define UT_VEC K0BASE // utlbmiss vector
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#define R_VEC (K1BASE + 0x1FC00000) // reset vector
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#define XUT_VEC (K0BASE + 0x80) // extended address tlbmiss
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#define ECC_VEC (K0BASE + 0x100) // Ecc exception vector
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#define E_VEC (K0BASE + 0x180) // Gen. exception vector
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// Address conversion macros
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#define K0_TO_K1(x) (U32(x) | 0xA0000000) // kseg0 to kseg1
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#define K1_TO_K0(x) (U32(x) & 0x9FFFFFFF) // kseg1 to kseg0
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#define K0_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg0 to physical
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#define K1_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg1 to physical
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#define KDM_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // direct mapped to physical
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#define PHYS_TO_K0(x) (U32(x) | 0x80000000) // physical to kseg0
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#define PHYS_TO_K1(x) (U32(x) | 0xA0000000) // physical to kseg1
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// Address predicates
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#define IS_KSEG0(x) (U32(x) >= K0BASE && U32(x) < K1BASE)
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#define IS_KSEG1(x) (U32(x) >= K1BASE && U32(x) < K2BASE)
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#define IS_KSEGDM(x) (U32(x) >= K0BASE && U32(x) < K2BASE)
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#define IS_KSEG2(x) (U32(x) >= K2BASE && U32(x) < KPTE_SHDUBASE)
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#define IS_KPTESEG(x) (U32(x) >= KPTE_SHDUBASE)
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#define IS_KUSEG(x) (U32(x) < K0BASE)
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// TLB size constants
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#define NTLBENTRIES 31 /* entry 31 is reserved by rdb */
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#define TLBHI_VPN2MASK 0xFFFFE000
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#define TLBHI_VPN2SHIFT 13
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#define TLBHI_PIDMASK 0xFF
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#define TLBHI_PIDSHIFT 0
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#define TLBHI_NPID 255 // 255 to fit in 8 bits
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#define TLBLO_PFNMASK 0x3FFFFFC0
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#define TLBLO_PFNSHIFT 6
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#define TLBLO_CACHMASK 0x38 // cache coherency algorithm
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#define TLBLO_CACHSHIFT 3
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#define TLBLO_UNCACHED 0x10 // not cached
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#define TLBLO_NONCOHRNT 0x18 // Cacheable non-coherent
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#define TLBLO_EXLWR 0x28 // Exclusive write
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#define TLBLO_D 0x4 // writeable
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#define TLBLO_V 0x2 // valid bit
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#define TLBLO_G 0x1 // global access bit
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#define TLBINX_PROBE 0x80000000
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#define TLBINX_INXMASK 0x3F
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#define TLBINX_INXSHIFT 0
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#define TLBRAND_RANDMASK 0x3F
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#define TLBRAND_RANDSHIFT 0
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#define TLBWIRED_WIREDMASK 0x3F
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#define TLBCTXT_BASEMASK 0xFF800000
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#define TLBCTXT_BASESHIFT 23
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#define TLBCTXT_BASEBITS 9
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#define TLBCTXT_VPNMASK 0x7FFFF0
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#define TLBCTXT_VPNSHIFT 4
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#define TLBPGMASK_4K 0x0
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#define TLBPGMASK_16K 0x6000
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#define TLBPGMASK_64K 0x1E000
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/*
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* Status register
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*/
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#define SR_CUMASK 0xF0000000 // coproc usable bits
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#define SR_CU3 0x80000000 // Coprocessor 3 usable
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#define SR_CU2 0x40000000 // Coprocessor 2 usable
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#define SR_CU1 0x20000000 // Coprocessor 1 usable
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#define SR_CU0 0x10000000 // Coprocessor 0 usable
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#define SR_RP 0x08000000 // Reduced power (quarter speed)
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#define SR_FR 0x04000000 // MIPS III FP register mode
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#define SR_RE 0x02000000 // Reverse endian
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#define SR_ITS 0x01000000 // Instruction trace support
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#define SR_BEV 0x00400000 // Use boot exception vectors
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#define SR_TS 0x00200000 // TLB shutdown
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#define SR_SR 0x00100000 // Soft reset occured
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#define SR_CH 0x00040000 // Cache hit for last 'cache' op
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#define SR_CE 0x00020000 // Create ECC
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#define SR_DE 0x00010000 // ECC of parity does not cause error
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// Interrupt enable bits
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// (NOTE: bits set to 1 enable the corresponding level interrupt)
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#define SR_IMASK 0x0000FF00 // Interrupt mask
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#define SR_IMASK8 0x00000000 // mask level 8
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#define SR_IMASK7 0x00008000 // mask level 7
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#define SR_IMASK6 0x0000C000 // mask level 6
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#define SR_IMASK5 0x0000E000 // mask level 5
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#define SR_IMASK4 0x0000F000 // mask level 4
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#define SR_IMASK3 0x0000F800 // mask level 3
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#define SR_IMASK2 0x0000FC00 // mask level 2
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#define SR_IMASK1 0x0000FE00 // mask level 1
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#define SR_IMASK0 0x0000FF00 // mask level 0
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#define SR_IBIT8 0x00008000 // bit level 8
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#define SR_IBIT7 0x00004000 // bit level 7
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#define SR_IBIT6 0x00002000 // bit level 6
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#define SR_IBIT5 0x00001000 // bit level 5
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#define SR_IBIT4 0x00000800 // bit level 4
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#define SR_IBIT3 0x00000400 // bit level 3
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#define SR_IBIT2 0x00000200 // bit level 2
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#define SR_IBIT1 0x00000100 // bit level 1
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#define SR_IMASKSHIFT 8
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#define SR_KX 0x00000080 // extended-addr TLB vec in kernel
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#define SR_SX 0x00000040 // xtended-addr TLB vec supervisor
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#define SR_UX 0x00000020 // xtended-addr TLB vec in user mode
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#define SR_KSU_MASK 0x00000018 // mode mask
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#define SR_KSU_USR 0x00000010 // user mode
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#define SR_KSU_SUP 0x00000008 // supervisor mode
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#define SR_KSU_KER 0x00000000 // kernel mode
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#define SR_ERL 0x00000004 // Error level, 1=>cache error
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#define SR_EXL 0x00000002 // Exception level, 1=>exception
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#define SR_IE 0x00000001 // interrupt enable, 1=>enable
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// Cause Register
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#define CAUSE_BD 0x80000000 // Branch delay slot
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#define CAUSE_CEMASK 0x30000000 // coprocessor error
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#define CAUSE_CESHIFT 28
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// Interrupt pending bits
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#define CAUSE_IP8 0x00008000 // External level 8 pending - COMPARE
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#define CAUSE_IP7 0x00004000 // External level 7 pending - INT4
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#define CAUSE_IP6 0x00002000 // External level 6 pending - INT3
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#define CAUSE_IP5 0x00001000 // External level 5 pending - INT2
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#define CAUSE_IP4 0x00000800 // External level 4 pending - INT1
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#define CAUSE_IP3 0x00000400 // External level 3 pending - INT0
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#define CAUSE_SW2 0x00000200 // Software level 2 pending
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#define CAUSE_SW1 0x00000100 // Software level 1 pending
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#define CAUSE_IPMASK 0x0000FF00 // Pending interrupt mask
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#define CAUSE_IPSHIFT 8
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#define CAUSE_EXCMASK 0x0000007C // Cause code bits
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#define CAUSE_EXCSHIFT 2
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// Cause register exception codes
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#define EXC_CODE(x) ((x) << 2)
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// Hardware exception codes
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#define EXC_INT EXC_CODE(0) // interrupt
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#define EXC_MOD EXC_CODE(1) // TLB mod
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#define EXC_RMISS EXC_CODE(2) // Read TLB Miss
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#define EXC_WMISS EXC_CODE(3) // Write TLB Miss
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#define EXC_RADE EXC_CODE(4) // Read Address Error
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#define EXC_WADE EXC_CODE(5) // Write Address Error
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#define EXC_IBE EXC_CODE(6) // Instruction Bus Error
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#define EXC_DBE EXC_CODE(7) // Data Bus Error
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#define EXC_SYSCALL EXC_CODE(8) // SYSCALL
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#define EXC_BREAK EXC_CODE(9) // BREAKpoint
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#define EXC_II EXC_CODE(10) // Illegal Instruction
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#define EXC_CPU EXC_CODE(11) // CoProcessor Unusable
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#define EXC_OV EXC_CODE(12) // OVerflow
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#define EXC_TRAP EXC_CODE(13) // Trap exception
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#define EXC_VCEI EXC_CODE(14) // Virt. Coherency on Inst. fetch
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#define EXC_FPE EXC_CODE(15) // Floating Point Exception
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#define EXC_WATCH EXC_CODE(23) // Watchpoint reference
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#define EXC_VCED EXC_CODE(31) // Virt. Coherency on data read
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// C0_PRID Defines
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#define C0_IMPMASK 0xFF00
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#define C0_IMPSHIFT 8
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#define C0_REVMASK 0xFF
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#define C0_MAJREVMASK 0xF0
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#define C0_MAJREVSHIFT 4
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#define C0_MINREVMASK 0xF
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// Coprocessor 0 operations
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#define C0_READI 0x1 // read ITLB entry addressed by C0_INDEX
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#define C0_WRITEI 0x2 // write ITLB entry addressed by C0_INDEX
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#define C0_WRITER 0x6 // write ITLB entry addressed by C0_RAND
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#define C0_PROBE 0x8 // probe for ITLB entry addressed by TLBHI
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#define C0_RFE 0x10 // restore for exception
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// 'cache' instruction definitions
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// Target cache
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#define CACH_PI 0x0 // specifies primary inst. cache
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#define CACH_PD 0x1 // primary data cache
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#define CACH_SI 0x2 // secondary instruction cache
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#define CACH_SD 0x3 // secondary data cache
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// Cache operations
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#define C_IINV 0x0 // index invalidate (inst, 2nd inst)
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#define C_IWBINV 0x0 // index writeback inval (d, sd)
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#define C_ILT 0x4 // index load tag (all)
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#define C_IST 0x8 // index store tag (all)
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#define C_CDX 0xC // create dirty exclusive (d, sd)
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#define C_HINV 0x10 // hit invalidate (all)
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#define C_HWBINV 0x14 // hit writeback inv. (d, sd)
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#define C_FILL 0x14 // fill (i)
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#define C_HWB 0x18 // hit writeback (i, d, sd)
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#define C_HSV 0x1C // hit set virt. (si, sd)
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// Cache size definitions
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#define ICACHE_SIZE 0x4000 // 16K
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#define ICACHE_LINESIZE 32 // 8 words
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#define ICACHE_LINEMASK (ICACHE_LINESIZE - 1)
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#define DCACHE_SIZE 0x2000 // 8K
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#define DCACHE_LINESIZE 16 // 4 words
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#define DCACHE_LINEMASK (DCACHE_LINESIZE - 1)
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// C0_CONFIG register definitions
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#define CONFIG_CM 0x80000000 // 1 == Master-Checker enabled
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#define CONFIG_EC 0x70000000 // System Clock ratio
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#define CONFIG_EC_1_1 0x6 // System Clock ratio 1 :1
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#define CONFIG_EC_3_2 0x7 // System Clock ratio 1.5 :1
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#define CONFIG_EC_2_1 0x0 // System Clock ratio 2 :1
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#define CONFIG_EC_3_1 0x1 // System Clock ratio 3 :1
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#define CONFIG_EP 0x0F000000 // Transmit Data Pattern
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#define CONFIG_SB 0x00C00000 // Secondary cache block size
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#define CONFIG_SS 0x00200000 // Split scache: 0 == I&D combined
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#define CONFIG_SW 0x00100000 // scache port: 0==128, 1==64
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#define CONFIG_EW 0x000C0000 // System Port width: 0==64, 1==32
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#define CONFIG_SC 0x00020000 // 0 -> 2nd cache present
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#define CONFIG_SM 0x00010000 // 0 -> Dirty Shared Coherency enable
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#define CONFIG_BE 0x00008000 // Endian-ness: 1 --> BE
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#define CONFIG_EM 0x00004000 // 1 -> ECC mode, 0 -> parity
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#define CONFIG_EB 0x00002000 // Block order:1->sequent,0->subblock
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#define CONFIG_IC 0x00000E00 // Primary Icache size
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#define CONFIG_DC 0x000001C0 // Primary Dcache size
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#define CONFIG_IB 0x00000020 // Icache block size
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#define CONFIG_DB 0x00000010 // Dcache block size
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#define CONFIG_CU 0x00000008 // Update on Store-conditional
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#define CONFIG_K0 0x00000007 // K0SEG Coherency algorithm
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#define CONFIG_UNCACHED 0x00000002 // K0 is uncached
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#define CONFIG_NONCOHRNT 0x00000003
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#define CONFIG_COHRNT_EXLWR 0x00000005
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#define CONFIG_SB_SHFT 22 // shift SB to bit position 0
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#define CONFIG_IC_SHFT 9 // shift IC to bit position 0
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#define CONFIG_DC_SHFT 6 // shift DC to bit position 0
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#define CONFIG_BE_SHFT 15 // shift BE to bit position 0
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// C0_TAGLO definitions for setting/getting cache states and physaddr bits
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#define SADDRMASK 0xFFFFE000 // 31..13 -> scache paddr bits 35..17
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#define SVINDEXMASK 0x00000380 // 9..7: prim virt index bits 14..12
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#define SSTATEMASK 0x00001C00 // bits 12..10 hold scache line state
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#define SINVALID 0x00000000 // invalid --> 000 == state 0
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#define SCLEANEXCL 0x00001000 // clean exclusive --> 100 == state 4
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#define SDIRTYEXCL 0x00001400 // dirty exclusive --> 101 == state 5
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#define SECC_MASK 0x0000007F // low 7 bits are ecc for the tag
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#define SADDR_SHIFT 4 // shift STagLo (31..13) to 35..17
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#define PADDRMASK 0xFFFFFF00 // PTagLo31..8->prim paddr bits35..12
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#define PADDR_SHIFT 4 // roll bits 35..12 down to 31..8
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#define PSTATEMASK 0x00C0 // bits 7..6 hold primary line state
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#define PINVALID 0x0000 // invalid --> 000 == state 0
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#define PCLEANEXCL 0x0080 // clean exclusive --> 10 == state 2
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#define PDIRTYEXCL 0x00C0 // dirty exclusive --> 11 == state 3
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#define PPARITY_MASK 0x0001 // low bit is parity bit (even).
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// C0_CACHE_ERR definitions.
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#define CACHERR_ER 0x80000000 // 0: inst ref, 1: data ref
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#define CACHERR_EC 0x40000000 // 0: primary, 1: secondary
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#define CACHERR_ED 0x20000000 // 1: data error
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#define CACHERR_ET 0x10000000 // 1: tag error
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#define CACHERR_ES 0x08000000 // 1: external ref, e.g. snoo
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#define CACHERR_EE 0x04000000 // error on SysAD bus
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#define CACHERR_EB 0x02000000 // complicated, see spec.
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#define CACHERR_EI 0x01000000 // complicated, see spec.
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#define CACHERR_SIDX_MASK 0x003FFFF8 // secondary cache index
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#define CACHERR_PIDX_MASK 0x00000007 // primary cache index
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#define CACHERR_PIDX_SHIFT 12 // bits 2..0 are paddr14..12
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/*
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* R4000 family supports hardware watchpoints:
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* C0_WATCHLO:
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* bits 31..3 are bits 31..3 of physaddr to watch
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* bit 2: reserved; must be written as 0.
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* bit 1: when set causes a watchpoint trap on load accesses to paddr.
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* bit 0: when set traps on stores to paddr;
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* C0_WATCHHI
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* bits 31..4 are reserved and must be written as zeros.
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* bits 3..0 are bits 35..32 of the physaddr to watch
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*/
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#define WATCHLO_WTRAP 0x00000001
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#define WATCHLO_RTRAP 0x00000002
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#define WATCHLO_ADDRMASK 0xFFFFFFF8
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#define WATCHLO_VALIDMASK 0xFFFFFFFB
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#define WATCHHI_VALIDMASK 0x0000000F
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// Coprocessor 0 registers
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#define C0_INX C_REG(0)
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#define C0_RAND C_REG(1)
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#define C0_ENTRYLO0 C_REG(2)
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#define C0_ENTRYLO1 C_REG(3)
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#define C0_CONTEXT C_REG(4)
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#define C0_PAGEMASK C_REG(5) // page mask
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#define C0_WIRED C_REG(6) // # wired entries in tlb
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#define C0_BADVADDR C_REG(8)
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#define C0_COUNT C_REG(9) // free-running counter
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#define C0_ENTRYHI C_REG(10)
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#define C0_COMPARE C_REG(11) // counter comparison reg.
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#define C0_SR C_REG(12)
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#define C0_CAUSE C_REG(13)
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#define C0_EPC C_REG(14)
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#define C0_PRID C_REG(15) // revision identifier
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#define C0_CONFIG C_REG(16) // hardware configuration
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#define C0_LLADDR C_REG(17) // load linked address
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#define C0_WATCHLO C_REG(18) // watchpoint
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#define C0_WATCHHI C_REG(19) // watchpoint
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#define C0_ECC C_REG(26) // S-cache ECC and primary parity
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#define C0_CACHE_ERR C_REG(27) // cache error status
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#define C0_TAGLO C_REG(28) // cache operations
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#define C0_TAGHI C_REG(29) // cache operations
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#define C0_ERROR_EPC C_REG(30) // ECC error prg. counter
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// floating-point status register
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#define C1_FPCSR C_REG(31)
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#define FPCSR_FS 0x01000000 // flush denorm to zero
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#define FPCSR_C 0x00800000 // condition bit
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#define FPCSR_CE 0x00020000 // cause: unimplemented operation
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#define FPCSR_CV 0x00010000 // cause: invalid operation
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#define FPCSR_CZ 0x00008000 // cause: division by zero
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#define FPCSR_CO 0x00004000 // cause: overflow
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#define FPCSR_CU 0x00002000 // cause: underflow
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#define FPCSR_CI 0x00001000 // cause: inexact operation
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#define FPCSR_EV 0x00000800 // enable: invalid operation
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#define FPCSR_EZ 0x00000400 // enable: division by zero
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#define FPCSR_EO 0x00000200 // enable: overflow
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#define FPCSR_EU 0x00000100 // enable: underflow
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#define FPCSR_EI 0x00000080 // enable: inexact operation
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#define FPCSR_FV 0x00000040 // flag: invalid operation
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#define FPCSR_FZ 0x00000020 // flag: division by zero
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#define FPCSR_FO 0x00000010 // flag: overflow
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#define FPCSR_FU 0x00000008 // flag: underflow
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#define FPCSR_FI 0x00000004 // flag: inexact operation
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#define FPCSR_RM_MASK 0x00000003 // rounding mode mask
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#define FPCSR_RM_RN 0x00000000 // round to nearest
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#define FPCSR_RM_RZ 0x00000001 // round to zero
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#define FPCSR_RM_RP 0x00000002 // round to positive infinity
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#define FPCSR_RM_RM 0x00000003 // round to negative infinity
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#endif
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